TLK1221 Datasheet, PDF (5/23 Pages) Texas Instruments – ETHERNET TRANSCEIVER

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Max Receive
Path Latency
31 Bit
Times
30 Bit
Times (Max)
TLK1221
SLLS713 – FEBRUARY 2007
INPUT DATA
K28.5 DXX.X DXX.X
K28.5 DXX.X DXX.X DXX.X
K28.5
RBC0
RBC1
RD(0–9)
Worst Case
Misaligned K28.5
Corrupt Data
DXX.X DXX.X K28.5 DXX.X DXX.X
K28.5
Misalignment Corrected
DXX.X DXX.X DXX.X
K28.5
SYNC
Figure 4. Word Realignment Timing Characteristic Waveforms
Systems that do not require framed data may disable byte alignment by tying SYNCEN low.
When a SYNC character is detected, the SYNC signal is brought high and is aligned with the K28.5 character.
The duration of the SYNC pulse is equal to the duration of the data.
Data Reception Latency
The serial-to-parallel data latency is the time from when the first bit arrives at the receiver until it is output in the
aligned parallel word with RD0 received as the first bit. The minimum latency in TBI mode is 21 bit times and the
maximum latency is 31 bit times.
RXP, RXN
10-Bit Code
t_{d(Rx latency)}
RD(0–9)
10-Bit Code
RBC0
RBC1
Figure 5. Receiver Latency, TBI Half-Rate Mode Shown
Testability
The loopback function provides for at-speed testing of the transmit/receive section of the circuitry. The enable
function allows for all circuitry to be disabled so that an Iddq test can be performed. The PRBS function also
allows for built-in self-test (BIST).
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