TLK1221 Datasheet, PDF (1/23 Pages) Texas Instruments – ETHERNET TRANSCEIVER

TLK1221
www.ti.com
ETHERNET TRANSCEIVER
SLLS713 – FEBRUARY 2007
FEATURES
• 0.6- to 1.3-Gigabits Per Second (Gbps)
Serializer/Deserializer
• Low Power Consumption 250 mW (typ) at 1.25
Gbps
• LVPECL-Compatible Differential I/O on
High-Speed Interface
• Single Monolithic PLL Design
• Support For 10-Bit Interface
• Receiver Differential-Input Thresholds,
200-mV Minimum
• Industrial Temperature Range From –40°C to
85°C
• IEEE 802.3 Gigabit Ethernet Compliant
• Designed in 0.25 µm CMOS Technology
• No External Filter Capacitors Required
• Comprehensive Suite of Built-In Testability
• 2.5-V Supply Voltage for Lowest-Power
Operation
• 3.3-V Tolerant on LVTTL Inputs
• Hot Plug Protection
• 40-Pin 6-mm × 6-mm QFN PowerPAD™
Package
RHA Package
(Top View)
ENABLE
TD0
TD1
TD2
TD3
VDD
TD4
TD5
TD6
TD7
40 39 38 37 36 35 34 33 32 31
1
30
2
29
3
28
4
27
5
26
GND
6
25
7
24
8
23
9
22
10
21
11 12 13 14 15 16 17 18 19 20
SYNC
RD0
RD1
RD2
VDD
RD3
RD4
RD5
RD6
RD7
DESCRIPTION
The TLK1221 gigabit Ethernet transceiver provides for high-speed full-duplex point-to-point data transmissions.
These devices are based on the timing requirements of the 10-bit interface specification by the IEEE 802.3
Gigabit Ethernet specification. The TLK1221 supports data rates from 0.6 Gbps through 1.3 Gbps.
The primary application of these devices is to provide building blocks for point-to-point baseband data
transmission over controlled-impedance media of 50 Ω. The transmission media can be printed-circuit board
traces, copper cables or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon
the attenuation characteristics of the media and the noise coupling to the environment.
The TLK1221 performs the data serialization, deserialization, and clock extraction functions for a physical layer
interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1 Gbps of data bandwidth over
a copper or optical media interface.
This device supports the defined 10-bit interface (TBI). In the TBI mode, the serializer/deserializer (SERDES)
accepts 10-bit wide 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted
differentially at PECL-compatible voltage levels. The SERDES extracts clock information from the input serial
stream and deserializes the data, outputting a parallel 10-bit data byte.
A comprehensive series of built-in tests is provided for self-test purposes, including loopback and pseudorandom
binary sequence (PRBS) generation and verification.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated