DAC3484_15 Datasheet, PDF (9/107 Pages) Texas Instruments – DAC3484 Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)

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DAC3484
SLAS749D – MARCH 2011 – REVISED SEPTEMBER 2015
NAME
AVDD
ALARM
BIASJ
CLKVDD
D[15..0]P
D[15..0]N
DACCLKP
DACCLKN
DACVDD
DATACLKP
DATACLKN
DIGVDD
EXTIO
FRAMEP
FRAMEN
GND
IOUTAP
IOUTAN
IOUTBP
IOUTBN
IOUTCP
PIN
NO.
D10, E11, F11, G11,
H11, J11, K11, L10
N12
H12
C12
N4, N3, N2, N1, M2, L2,
K2, J2, F2, E2, D2, C2,
A1, A2, A3, A4
P4, P3, P2, P1, M1, L1,
K1, J1, F1, E1, D1, C1,
B1, B2, B3, B4
A12
A11
D9, E9, E10, F10, G10,
H10, J10, K9, K10, L9
G2
G1
E5, E6, E7, F5, J5, K5,
K6, K7
G12
H2
H1
A10, A13, A14, B10,
B11, B12, B13, C5, C6,
C7, C8, C9, C10, C13,
D8, D13, D14, E8, E12,
E13, F6, F7, F8, F9,
F12, F13, G6, G7, G8,
G9, G13, G14, H6, H7,
H8, H9, H13, H14, J6,
J7, J8, J9, J12, J13, K8,
K13, L8, L13, L14, M5,
M6, M7, M8, M9, M10,
M11, M12, M13, N13,
P13, P14
B14
C14
F14
E14
J14
Pin Functions - NFBGA
I/O
DESCRIPTION
I Analog supply voltage. (3.3 V)
CMOS output for ALARM condition. The ALARM output functionality is defined through the
O config7 register. Default polarity is active low, but can be changed to active high via
config0 alarm_out_pol control bit.
Full-scale output current bias. For 30-mA full-scale output current, connect 1.28 kΩ to
O ground. Change the full-scale output current through coarse_dac(3:0) in config3,
bit<15:12>
I
Internal clock buffer supply voltage. (1.2 V)
It is recommended to isolate this supply from DIGVDD and DACVDD.
LVDS positive input data bits 0 through 15. Internal 100-Ω termination resistor. Data
format relative to DATACLKP/N clock is Double Data Rate (DDR).
I
D15P is most significant data bit (MSB)
D0P is least significant data bit (LSB)
The order of the bus can be reversed via config2 revbus bit.
I LVDS negative input data bits 0 through 15. (See D[15:0]P description above)
I Positive external LVPECL clock input for DAC core with a self-bias.
I
Complementary external LVPECL clock input for DAC core. (see the DACCLKP
description)
I
DAC core supply voltage. (1.2 V). It is recommended to isolate this supply from CLKVDD
and DIGVDD.
I
LVDS positive input data clock. Internal 100-Ω termination resistor. Input data D[15:0]P/N
is latched on both edges of DATACLKP/N (Double Data Rate).
I LVDS negative input data clock. (See DATACLKP description)
I
Digital supply voltage. (1.2 V). It is recommended to isolate this supply from CLKVDD and
DACVDD.
Used as external reference input when internal reference is disabled through config27
I/O
extref_ena = 1b. Used as internal reference output when config27 extref_ena = 0b
(default). Requires a 0.1-µF decoupling capacitor to AGND when used as reference
output.
LVDS frame indicator positive input. Internal 100-Ω termination resistor.
The main functions of this input are to reset the FIFO pointer or to be used as a syncing
I
source. These two functions are captured with the rising edge of DATACLKP/N. The signal
captured by the falling edge of DATACLKP/N can be used as a block parity bit. The
FRAMEP/N signal should be edge-aligned with D[15:0]P/N.
Additionally it is used to indicate the beginning of the frame.
I LVDS frame indicator negative input. (See the FRAMEP description)
I These pins are ground for all supplies.
O A-Channel DAC current output. Connect directly to ground if unused.
O A-Channel DAC complementary current output. Connect directly to ground if unused.
O B-Channel DAC current output. Connect directly to ground if unused.
O B-Channel DAC complementary current output. Connect directly to ground if unused.
O C-Channel DAC current output. Connect directly to ground if unused.
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