DAC3484_15 Datasheet, PDF (81/107 Pages) Texas Instruments – DAC3484 Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)

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DAC3484
SLAS749D – MARCH 2011 – REVISED SEPTEMBER 2015
Register
Name
config41
Address
0x29
Table 53. Register Name: config41 – Address: 0x29, Default: 0x1A1A
Bit
Name
Function
15:0 iotest_pattern4 Dataword4 in the IO test pattern. It is used with the seven other words to test the input data.
Default
Value
0x1A1A
Register
Name
config42
Address
0x2A
Table 54. Register Name: config42 – Address: 0x2A, Default: 0x1616
Bit
Name
15:0 iotest_pattern5
Function
Dataword5 in the IO test pattern. It is used with the seven other words to test the input
data.
Default
Value
0x1616
Register
Name
config43
Address
0x2B
Table 55. Register Name: config43 – Address: 0x2B, Default: 0xAAAA
Bit
Name
15:0 iotest_pattern6
Function
Dataword6 in the IO test pattern. It is used with the seven other words to test the input
data.
Default
Value
0xAAAA
Register
Name
config44
Table 56. Register Name: config44 – Address: 0x2C, Default: 0xC6C6
Address
0x2C
Bit
Name
15:0 iotest_pattern7
Function
Dataword7 in the IO test pattern. It is used with the seven other words to test the input
data.
Default
Value
0xC6C6
Register
Name
config45
Address
0x2D
Table 57. Register Name: config45 – Address: 0x2D, Default: 0x0004
Bit
Name
15 reserved
14 ostrtodig_sel
13 ramp_ena
12:1 Reserved
Function
Reserved for factory use
When set, the OSTR signal is passed directly to the digital block. This is the signal that
is used to clock the dividers.
When set, a ramp signal is inserted in the input data at the FIFO input.
Reserved for factory use.
0 sifdac_ena
When set, the DAC output is set to the value in sifdac(15:0) in register config48. In this
mode, sif_txena in config3 and TXENABLE inputs are ignored.
Default
Value
0
0
0
0000
0000
0010
0
Register
Name
config46
Address
0x2E
Table 58. Register Name: config46 – Address: 0x2E, Default: 0x0000
Bit
Name
15:8 grp_delayA(7:0)
7:0 grp_delayB(7:0)
Function
Sets the group delay function for DACA. The maximum delay ranges from 30 ps to 100
ps and is dependent on DAC sample clock. Contact TI for specific application
information.
Sets the group delay function for DACB. The maximum delay ranges from 30 ps to 100
ps and is dependent on DAC sample clock. Contact TI for specific application
information.
Default
Value
0x00
0x00
Register
Name
config47
Address
0x2F
Table 59. Register Name: config47 – Address: 0x2F, Default: 0x0000
Bit
Name
15:8 grp_delayC(7:0)
7:0
grp_delayD(7:0)
Function
Sets the group delay function for DACC. The maximum delay ranges from 30 ps to
100 ps and is dependent on DAC sample clock. Contact TI for specific application
information.
Sets the group delay function for DACD. The maximum delay ranges from 30 ps to
100 ps and is dependent on DAC sample clock. Contact TI for specific application
information.
Default
Value
0x00
0x00
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