DAC3484_15 Datasheet, PDF (62/107 Pages) Texas Instruments – DAC3484 Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)

DAC3484
SLAS749D – MARCH 2011 – REVISED SEPTEMBER 2015
Device Functional Modes (continued)
DACCLKP/N
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FPGA
LVPECL Outputs
Clock Generator
LVPECL Outputs
PLL/
DLL
D[15:0]P/N
FRAMEP/N
Delay 1
DATACLKP/N
DAC3484 DAC1
D[15:0]P/N
Variable delays due to variations in the FPGA(s) output
paths or board level wiring or temperature/voltage deltas
FRAMEP/N
Delay 2
DATACLKP/N
DAC3484 DAC2
Variation in both the FIFO
Out clock cycles and DAC
clock cycles
DACCLKP/N
Figure 90. Multi-Device Operation in Single Sync Source Mode
B0456-03
7.5 Programming
7.5.1 Power-Up Sequence
The following startup sequence is recommended to power-up the DAC3484:
1. Set TXENABLE low
2. Supply all 1.2-V voltages (DACVDD, DIGVDD, CLKVDD, and VFUSE) and all 3.3-V voltages (AVDD,
IOVDD, and PLLAVDD). The 1.2-V and 3.3-V supplies can be powered up simultaneously or in any order.
There are no specific requirements on the ramp rate for the supplies.
3. Provide all LVPECL inputs: DACCLKP/N and the optional OSTRP/N. These inputs can also be provided after
the SIF register programming.
4. Toggle the RESETB pin for a minimum 25 ns active low pulse width.
5. Program the SIF registers.
6. Program fuse_sleep (config27, bit<11>) to put the internal fuses to sleep. To enable dual channel mode, set
Config1, bit <8> to 0b and Config16, bit<13:12> to 11b. This dual channel mode is functionally equivalent to
the dual channel DAC3484 (channels B and C active). See the DAC3484 SLAS748 datasheet for details.
7. FIFO configuration needed for synchronization:
(a) Program syncsel_fifoin(3:0) (config32, bits<15:12>) to select the FIFO input pointer sync source.
(b) Program syncsel_fifoout(3:0) (config32, bits<11:8>) to select the FIFO output pointer sync source.
(c) Program syncsel_dataformatter(1:0) (config31, bits<3:2>) to select the FIFO Data Formatter sync source.
8. Clock divider configuration needed for synchronization:
(a) Program clkdiv_sync_sel (config32, bit<0>) to select the clock divider sync source.
(b) Program clkdiv_sync_ena (config0, bit<2>) to 1b to enable clock divider sync.
(c) For multi-DAC synchronization in PLL mode, program pll_ndivsync_ena (config24, bit<11>) to 1b to
synchronize the PLL N-divider.
9. Provide all LVDS inputs (D[15:0]P/N, DATACLKP/N, FRAMEP/N, SYNCP/N, and PARITYP/N)
simultaneously. Synchronize the FIFO and clock divider by providing the pulse or periodic signals needed.
(a) For Single Sync Source Mode where either FRAMEP/N or SYNCP/N is used to sync the FIFO, a single
rising edge for FIFO, FIFO data formatter, and clock divider sync is recommended. Periodic sync signal
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