DAC3484_15 Datasheet, PDF (60/107 Pages) Texas Instruments – DAC3484 Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)

DAC3484
SLAS749D – MARCH 2011 – REVISED SEPTEMBER 2015
Device Functional Modes (continued)
DACCLKP/N(1)
OSTRP/N(1)
t_{SKEW ~ 0}
t_S(OSTR)
t_H(OSTR)
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DACCLKP/N(2)
OSTRP/N(2)
t_S(OSTR)
t_H(OSTR)
•
•
•
•
T0526-03
Figure 88. Timing Diagram for LVPECL Synchronization Signals
The following steps are required to ensure the devices are fully synchronized. The procedure assumes all the
DAC3484 devices have a DACCLK and OSTR signal and must be carried out on each device.
1. Start-up the device as described in the power-up sequence. Set the DAC3484 in Dual Sync Sources mode
and select OSTR as the clock divider sync source (clkdiv_sync_sel in register config32).
2. Sync the clock divider and FIFO pointers.
3. Verify there are no FIFO alarms either through register config5 or through the ALARM pin.
4. Disable clock divider sync by setting clkdiv_sync_ena to 0b in register config0.
After these steps all the DAC3484 outputs will be synchronized.
7.4.1.2 Multi-Device Synchronization: PLL Enabled with Dual Sync Sources Mode
The DAC3484 allows exact phase alignment between multiple devices even when operating with the internal PLL
clock multiplier. In PLL clock mode, the PLL generates the DAC clock and an internal OSTR signal from the
reference clock applied to the DACCLK inputs so there is no need to supply an additional LVPECL OSTR signal.
For this method to operate properly the SYNC signal should be set to reset the PLL N dividers to a known state
by setting pll_ndivsync_ena in register config24 to 1b. The SYNC signal resets the PLL N dividers with a rising
edge, and the timing relationship t_{s(SYNC_PLL)} and t_{h(SYNC_PLL)} are relative to the reference clock presented on the
DACCLK pin.
Both SYNC and DACCLK can be set as low frequency signals to greatly simplifying trace routing (SYNC can be
just a pulse as a single rising edge is required, if using a periodic signal it is recommended to clear the
pll_ndivsync_ena bit after resetting the PLL dividers). Besides the t_{s(SYNC_PLL)} and t_{h(SYNC_PLL)} requirement
between SYNC and DACCLK, there is no additional required timing relationship between the SYNC and FRAME
signals or between DACCLK and DATACLK. The only restriction as in the PLL disabled case is that the DACCLK
and SYNC signals are distributed from device to device with the lowest skew possible.
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