BQ24742 Datasheet, PDF (9/35 Pages) Texas Instruments – Li-Ion or Li-Polymer Battery Charger with Low Iq and Accurate Trickle Charge

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bq24741, bq24742
SLUS875B – MARCH 2009 – REVISED OCTOBER 2009
ELECTRICAL CHARACTERISTICS (continued)
9.0 V ≤ V_PVCC ≤ 24 V, 0°C < T_J < +125°C, F_s=600 kHz, typical values are at T_A = 25°C, with respect to AGND (unless
otherwise noted) ^{(1) (2) (3)}
PARAMETER
TEST CONDITIONS
PWM LOW SIDE DRIVER (LODRV)
R_{DS_LO_ON}
Low side driver turn-on resistance
R_{DS_LO_OFF}
Low side driver turn-off resistance
PWM DRIVERS TIMING
REGN = 6 V, tested at 100 mA
REGN = 6 V, tested at 100 mA
Driver Dead Time between HIDRV and
LODRV
PWM OSCILLATOR
F_S
Programmable PWM switching frequency R_FSET=130 kΩ - 45 kΩ
range
PWM switching frequency accuracy
RAMP amplitude
DC offset of RAMP
QUIESCENT CURRENT
I_{OFF_STATE}
Total off-state quiescent current into pins: V_BAT = 16.8 V, V_ACDET < 0.6 V,
CSP, CSN, BAT, BTST, SW, PVCC, ACP, V_PVCC > 8 V, T_J = 0 to 125°C
ACN
I_{BAT_ON}
I_{BATQ_CD}
Total off-state battery current from ACP,
ACN
Battery on-state quiescent current
Total quiescent current into CSP, CSN,
BAT, PVCC, BTST, SW
V_BAT = 16.8 V, V_ACDET < 0.6 V,
V_PVCC > 8 V, T_J = 0 to 125°C
V_BAT = 16.8 , 0.6 V < V_ACDET < 2.4 V,
V_PVCC > 8V
Adapter present, V_ACDET > 2.4 V, charge disabled
I_AC
Adapter quiescent current
INTERNAL SOFT START (8 steps to regulation current)
V_PVCC = 20 V, charge disabled
Soft start steps
Soft start time of each step (512 PWM
cycles)
LOGIC INPUT PIN CHARACTERISTICS (CE, TRICKLE)
V_{IN_LO}
Input low threshold voltage
V_{IN_HI}
Input high threshold voltage
R_PULLDOWN
T_{CE_ENCHARGE}
PIN pull down resistance inside IC
Delay from CE=HIGH to charge enable⁽⁶⁾
LOGIC INPUT PIN CHARACTERISTICS (CELLS)
V = 0 to V_REGN
F_s=300 kHz - 800 kHz
V_{IN_LO}
V_{IN_FLOAT}
Input low threshold voltage, 3 cells
Input float threshold voltage, 2 cells
CELLS voltage falling edge
CELLS voltage rising for MIN,
CELLS voltage falling for MAX
V_{IN_HI}
Input high threshold voltage, 4 cells
CELLS voltage rising
I_{BIAS_FLOAT}
Input bias float current for 2 cell selection VCE = 0 to VREGN
OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS ( EXTPWR, DPMDET, LPMOD)
V_{OUT_LO}
Output low saturation voltage
Leakage current
Sink Current = 5 mA
Pull up to 3.3 v
DPMDET delay, both edge
MIN TYP MAX
6
1.2
25
300
800
-20%
1.33
300
20%
7
11
1
1
100
200
1
1.5
8
853
0.8
2.1
1
2
0.5
0.8
1.8
2.5
–1
1
0.5
1
5
(6) Verified by design
UNIT
Ω
Ω
ns
kHz
V
mV
μA
μA
mA
μA
mA
step
μs
V
MΩ
ms
V
μA
V
μA
ms
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