BQ24742 Datasheet, PDF (5/35 Pages) Texas Instruments – Li-Ion or Li-Polymer Battery Charger with Low Iq and Accurate Trickle Charge

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bq24741, bq24742
SLUS875B – MARCH 2009 – REVISED OCTOBER 2009
Table 1. Pin Functions – 28-Pin QFN (continued)
PIN
NAME
NO.
DPMDET 21
PGND
22
LODRV 23
REGN
24
SW
25
HIDRV
26
BTST
27
PVCC
28
PowerPad
DESCRIPTION
Dynamic power management (DPM) input current loop active, open-drain output status. Logic low (LO) indicates input
current is being limited by reducing the charge current. Connect 10-kohm pull-up resistor from DPMDET pin to VREF or
a different pull-up supply rail.
Power ground. Ground connection for high-current power converter node. On PCB layout, connect directly to source of
low-side power MOSFET, to ground connection of in put and output capacitors of the charger. Only connect to AGND
through the PowerPad underneath the IC.
PWM low side driver output. Connect to the gate of the low–side power MOSFET with a short and wide trace.
PWM low side driver positive supply output. Connect a 1 μF ceramic capacitor from REGN to PGND pin, close to the
IC. Use for low side driver and high-side driver bootstrap voltage by connecting a small signal Schottky diode from
REGN to BTST. REGN is disabled when CE is LOW.
PWM high side driver negative supply. Connect to the Phase switching node (junction of the low-side power MOSFET
drain, high-side power MOSFET source, and output inductor). Connect the 0.1 μF bootstrap capacitor from SW to
BTST.
PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.
PWM high side driver positive supply. Connect a 0.1 μF bootstrap ceramic capacitor from BTST to SW. Connect a
bootstrap Schottky diode from REGN to BTST. A optional 2.0Ω - 5.1Ω bootstrap resistor can be inserted between the
BTST pin and the common point of the bootstrap capacitor and bootstrap diode, thus dampening the SW node voltage
ring and spike.
IC power positive supply. Connect to the adapter input through a schottky diode. Place a 0.1 uF ceramic capacitor from
PVCC to PGND pin close to the IC.
Exposed pad beneath the IC. AGND and PGND star-connected only at the PowerPad plane. Always solder PowerPad
to the board, and have vias on the PowerPad plane connecting to AGND and PGND planes. It also serves as a thermal
pad to dissipate the heat.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)^{(1) (2)}
Voltage range
Maximum difference voltage
Junction temperature range
Storage temperature range
PVCC, ACP, ACN, CSP, CSN, BAT
SW
REGN, LODRV, VADJ, ACSET, ISET, ACDET, FSET, IADAPT, LPMOD,
LPREF, CE, CELLS, EXTPWR, DPMDET, TRICKLE
VDAC, VREF
BTST, HIDRV with respect to AGND and PGND
AGND, PGND
ACP–ACN, CSP–CSN
VALUE
–0.3 to 30
–1 to 30
–0.3 to 7
–0.3 to 3.6
–0.3 to 36
–1 to 1
-0.5 to 0.5
–40 to 155
–55 to 155
UNIT
V
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
Copyright © 2009, Texas Instruments Incorporated
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