BQ24742 Datasheet, PDF (17/35 Pages) Texas Instruments – Li-Ion or Li-Polymer Battery Charger with Low Iq and Accurate Trickle Charge

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bq24741, bq24742
SLUS875B – MARCH 2009 – REVISED OCTOBER 2009
DETAILED DESCRIPTION
Converter Operation
The synchronous buck PWM converter uses a programmable-frequency (300 kHz to 800 kHz) voltage mode
control scheme. A type III compensation network allows using ceramic capacitors at the output of the converter.
The compensation input stage is connected internally between the feedback output (FBO) and the error amplifier
input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error
amplifier output (EAO). The LC output filter should be selected to give a nominal resonant frequency within 8 kHz
to 12.5 kHz to have good loop compensation.
Where resonant frequency, f_o, is give by:
f_o =
1
2p L_oC_o
(1)
Where L_o, C_o are the total output filter inductance and capacitance
An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the
converter. The ramp height is fixed 1.33 V. The ramp is offset by 300 mV in order to allow zero percent
duty-cycle, when the EAO signal is below the ramp. The EAO signal is also allowed to exceed the saw-tooth
ramp signal in order to get a 100% duty-cycle PWM request. Internal gate drive logic allows achieving 99.98%
duty-cycle while ensuring the N-channel upper device always has enough voltage to stay fully on. If the BTST pin
to SW pin voltage falls below 4 V, then the high-side n-channel power MOSFET is turned off and the low-side
n-channel power MOSFET is turned on to pull the SW node down and recharge the BTST capacitor. Then the
high-side driver returns to 100% duty-cycle operation until the (BTST-SW) voltage is detected to fall low again
due to leakage current discharging the BTST capacitor below the 4 V, and the reset pulse is reissued.
The oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage,
charge current, and temperature, simplifying output filter design and keeping it out of the audible noise region.
The charge current sense resistor RSR should be placed with at least half or more of the total output capacitance
placed before the sense resistor contacting both sense resistor and the output inductor; and the other half or
remaining capacitance placed after the sense resistor. The output capacitance should be divided and placed
onto both sides of the charge current sense resistor. A ratio of 50:50 percent gives the best performance; but the
node in which the output inductor and sense resistor connect should have a minimum of 50% of the total
capacitance. This capacitance provides sufficient filtering to remove the switching noise and give better current
sense accuracy. The type III compensation provides Phase boost near the cross-over frequency, giving sufficient
Phase margin.
Synchronous and Non-Synchronous Operation
The charger operates in non-synchronous mode when the sensed charge current is below the charge
under-current comparator threshold (30 mV). Otherwise, the charger operates in synchronous mode. This part is
designed for 20 mΩ charge current sense resistor and the SYNC/NON-SYNC threshold is 1.5 A. If 10 mΩ is
used, the SYNC/NON-SYNC threshold will be 3 A.
During synchronous mode, the low-side n-channel power MOSFET is on, when the high-side n-channel power
MOSFET is off. The internal gate drive logic ensures there is break-before-make switching to prevent
shoot-through currents. During the 25 ns dead time where both FETs are off, the back-diode of the low-side
power MOSFET conducts the inductor current. Having the low-side FET turn-on keeps the power dissipation low,
and allows safely charging at high currents. During synchronous mode the inductor current is always flowing and
operates in Continuous Conduction Mode (CCM), creating a fixed two-pole system.
During non-synchronous operation, the low side MOSFET will stay off during the off-time unless the voltage on
the bootstrap capacitor drops below 4 V. If this occurs, the high side FET will be turned off and the 80ns low-side
MOSFET recharge pulse will be initiated. The 80 ns pulse pulls the SW node (connection between high and
low-side MOSFET) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value. After the 80
ns, the low-side MOSFET is kept off to prevent negative inductor current from occurring. The inductor current is
blocked by the off low-side MOSFET, and the inductor current will become discontinuous. This mode is called
Discontinuous Conduction Mode (DCM).
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