BQ24742 Datasheet, PDF (4/35 Pages) Texas Instruments – Li-Ion or Li-Polymer Battery Charger with Low Iq and Accurate Trickle Charge

bq24741, bq24742
SLUS875B – MARCH 2009 – REVISED OCTOBER 2009
www.ti.com
PIN
NAME
NO.
CE
1
ACN
2
ACP
3
LPMOD
4
ACDET
5
ACSET
6
LPREF
7
TRICKLE 8
AGND
9
VREF
10
VDAC
11
VADJ
12
EXTPWR 13
FSET
14
IADAPT 15
ISET
16
BAT
17
CSN
18
CSP
19
CELLS
20
Table 1. Pin Functions – 28-Pin QFN
DESCRIPTION
Charge-enable active-HIGH logic input. HI enables charge. LO disables charge. It has an internal 1 MΩ pull-down
resistor. A 10 KΩ external resistor is required to connect the CE pin to the external pull-up rail other than VREF.
Adapter current sense resistor, negative input. A 0.1 μF ceramic capacitor is placed from ACN to ACP to provide
differential-mode filtering. An optional 0.1 μF ceramic capacitor is placed from ACN pin to AGND for common-mode
filtering.
Adapter current sense resistor, positive input. A 0.1 μF ceramic capacitor is placed from ACN to ACP to provide
differential-mode filtering. A 0.1 μF ceramic capacitor is placed from ACP pin to AGND for common-mode filtering.
Low-power-mode-detect active-LOW open-drain logic output. Place a 10kohm pull-up resistor from LPMOD pin to the
pull-up voltage rail. The output is HI when IADAPT pin voltage is lower than LPREF pin voltage. The output is LOW
when IADAPT pin voltage is higher than LPREF pin voltage. Internal 6% hysteresis.
Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from adapter
input to ACDET pin to AGND pin. Adapter voltage is detected if ACDET pin voltage is greater than 2.4 V. IADAPT
current sense amplifier is active when ACDET pin voltage is greater than 0.6V and PVCC > VUVLO. ACOV is input
over-voltage protection; it disables charge when ACDET > 3.1 V. ACOV does not latch, and normal operation resumes
when ACDET < 3.1 V.
Adapter current set input. The voltage ratio of ACSET voltage versus VDAC voltage programs the input current
regulation set-point during Dynamic Power Management (DPM). Program by connecting a resistor divider from VDAC to
ACSET to AGND; or by connecting the output of an external DAC to the ACSET pin and connect the DAC supply to the
VDAC pin.
Low power voltage set input. Connect a resistor divider from VREF to LPREF, and AGND to program the reference for
the LOPWR comparator. The LPREF pin voltage is compared to the IADAPT pin voltage and the logic output is given
on the LPMOD open-drain pin. Connect LPREF to ACSET through a resistor divider to track the adapter power.
Trickle current enable logic input. When CE is HIGH, a HIGH level on this pin enables accurate 150 mA trickle charge
with 20 mΩ sense resistor. A LOW level on this pin enables the ISET pin to program the charge current. It has an
internal 1MΩ pull-down resistor.
Analog ground. Ground connection for low-current sensitive analog and digital signals. On PCB layout, connect to the
analog ground plane, and only connect to PGND through the PowerPad underneath the IC.
3.3 V regulated voltage output. Place a 1 μF ceramic capacitor from VREF to AGND pin close to the IC. This voltage
could be used for ratio-metric programming of voltage and current regulation and for programming the LPREF
threshold. VREF is also the voltage source for the internal circuit.
Charge voltage set reference input. Connect the VREF or external DAC voltage source to VDAC pin. Battery voltage,
charge current, and input current are programmed as a ratio of the VDAC pin voltage versus the voltage on VADJ, and
ACSET pin voltages, respectively. Place resistor dividers from VDAC to VADJ, ISET, and ACSET pins to AGND for
programming. A DAC could be used by connecting the DAC supply to VDAC and connecting the output to VADJ, ISET,
or ACSET.
Charge voltage set input. The voltage ratio of VADJ voltage versus VDAC voltage programs the battery voltage
regulation set-point. Program by connecting a resistor divider from VDAC to VADJ, to AGND; or, by connecting the
output of an external DAC to VADJ pin and connect the DAC supply to VDAC pin.
Valid adapter active-low detect logic open-drain output. Pulled LO when Input voltage is above ACDET programmed
threshold OR input current is greater than 1.25 A with 10 mΩ sense resistor. Connect a 10 kΩ pull-up resistor from
EXTPWR pin to pull-up supply rail.
PWM switching frequency (F_s) program pin. Program the switching frequency by placing a resistor to AGND on this pin.
Adapter current sense amplifier output. IADAPT voltage is 20 times the differential voltage across ACP-ACN. Place a
100pF (max) or less ceramic decoupling capacitor from IADAPT to AGND.
Charge current set input. The voltage ratio of ISET voltage versus VDAC voltage programs the charge current
regulation set-point. Program by connecting a resistor divider from VDAC to ISET, to AGND; or, by connecting the
output of an external DAC to ISET pin and connect the DAC supply to VDAC pin.
Battery voltage remote sense. Directly connect a kelvin sense trace from the battery pack positive terminal to the BAT
pin to accurately sense the battery pack voltage. Place a 0.1 μF capacitor from BAT to AGND close to the IC to filter
high frequency noise.
Charge current sense resistor, negative input. A 0.1 μF ceramic capacitor is placed from CSN to CSP to provide
differential-mode filtering. An optional 0.1 μF ceramic capacitor is placed from CSN pin to AGND for common-mode
filtering.
Charge current sense resistor, positive input. A 0.1 μF ceramic capacitor is placed from CSN to CSP to provide
differential-mode filtering. A 0.1 μF ceramic capacitor is placed from CSP pin to AGND for common-mode filtering.
2, 3 or 4 cells selection logic input. Logic Lo programs 3–cell. Logic HI programs 4-cell. Floating programs 2–cell.
4
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