BQ24742 Datasheet, PDF (26/35 Pages) Texas Instruments – Li-Ion or Li-Polymer Battery Charger with Low Iq and Accurate Trickle Charge

bq24741, bq24742
SLUS875B – MARCH 2009 – REVISED OCTOBER 2009
www.ti.com
To prevent unintentional charger shut down in normal operation, MOSFET R_DS(on) selection and PCB layout is
very important. Figure 33 shows a need improve PCB layout example and its equivalent circuit. In this layout,
system current path and charger input current path is not separated, as a result, the system current causes
voltage drop in the PCB copper and is sensed by IC. The worst layout is when a system current pull point is after
charger input; as a result all system current voltage drops are counted into over current protection comparator.
The worst case for IC is the total system current and charger input current sum equals DPM current. When
system pull more current, the charger IC tries to regulate R_AC current as a constant current by reducing charging
current.
RAC
System Path PCB Trace
System current
To ACP
To ACN
Charger input current
Charger Input PCB Trace
(a) PCB Layout
IDPM
RAC
R _PCB
ACP
ACN
ICHRGIN
Charger
(b) Equivalent Circuit
ISYS
IBAT
Figure 33. Need Improve PCB Layout Example
Figure 34 shows the optimized PCB layout example. The system current path and charge input current path is
separated, as a result the IC only senses charger input current caused PCB voltage drop and minimized the
possibility of unintentional charger shut down in normal operation. This also makes PCB layout easier for high
system current application.
RAC
System Path PCB Trace
System current
IDPM
ISYS
To ACP
To ACN
Single point connection at R AC
Charger input current
Charger Input PCB Trace
(a) PCB Layout
R _AC
R _PCB
ACP
ACN
ICHRGIN
Charger
(b) Equivalent Circuit
IBAT
Figure 34. Optimized PCB Layout Example
The total voltage drop sensed by IC can be express as the following equation.
( ( ) ) V_top = R_AC ´ I_DPM + R_PCB ´ I_CHRGIN + I_DPM - I_CHRGIN ´ k + R_DS(on) ´ I_PEAK
(17)
where the R_AC is the AC adapter current sensing resistance, I_DPM is the DPM current set point, R_PCB is the PCB
trace equivalent resistance, I_CHRGIN is the charger input current, k is the PCB factor, R_DS(on) is the high side
MOSFET turn on resistance and I_PEAK is the peak current of inductor. Here the PCB factor k equals 0 means the
best layout shown in Figure 34 where the PCB trace only goes through charger input current while k equals 1
means the worst layout shown in Figure 33 where the PCB trace goes through all the DPM current. The total
voltage drop must below the high side short circuit protection threshold to prevent unintentional charger shut
down in normal operation.
PCB Layout
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loop (see Figure 35) is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper
layout. Layout PCB according to this specific order is essential.
1. Place input capacitor as close as possible to switching MOSFET’s supply and ground connections and use
shortest copper trace connection. These parts should be placed on the same layer of PCB instead of on
different layers and using vias to make this connection.
2. The IC should be placed close to the switching MOSFET’s gate terminals and keep the gate drive signal
traces short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of switching
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