SM320C6713-EP_1 Datasheet, PDF (89/131 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SM320C6713-EP
SM320C6713B-EP
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Recommended Operating Conditions ⁽¹⁾ (continued)
V_US
Maximum voltage during undershoot (See Figure 11-5)
A version
T_C
Operating case temperature S version
M version
SGUS049I – AUGUST 2003 – REVISED SEPTEMBER 2009
MIN NOM MAX UNIT
–0.7⁽³⁾ V
–40
105
–55
105 °C
–55
125
11.3 Electrical Characteristics⁽¹⁾
over recommended ranges of supply voltage and operating case temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
V_OH
High-level output
voltage
All signals except SCL1, SDA1,
SCL0, and SDA0
I_OH = MAX
2.4
V
V_OL
Low-level output
voltage
I_I
Input current
All signals except SCL1, SDA1,
SCL0, and SDA0
SCL1, SDA1, SCL0, and SDA0
All signals except SCL1, SDA1,
SCL0, and SDA0
SCL1, SDA1, SCL0, and SDA0
I_OL = MAX
I_OL = MAX
V_I = V_SS to DV_DD
0.4
V
0.4
±170
μA
±10
All signals except SCL1, SDA1,
I_OZ Off-state output current ^{SCL0, and SDA0}
SCL1, SDA1, SCL0, and SDA0
V_O = DV_DD or 0 V
±170
μA
±10
I_DD2V Core supply current⁽²⁾
13GDPA, CV_DD = 1.4 V,
CPU clock = 300 MHz
13GDPA, CV_DD = 1.26 V,
CPU clock = 200 MHz
945
mA
560
I_DD3V I/O supply current⁽²⁾
C6713/13B, DV_DD = 3.3 V,
EMIF speed = 100 MHz
75
mA
C_I Input capacitance
C_o Output capacitance
7 pF
7 pF
(1) For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
(2) Measured with average activity (50% high/50% low power) at 25°C case temperature and 100-MHz EMIF. This model represents a
device performing high-DSP-activity operations 50% of the time, and the remainder performing low-DSP-activity operations. The
high/low-DSP-activity models are defined as follows:
High DSP activity model:
CPU: 8 instructions/cycle with 2 LDDW instructions [L1 data memory: 128 bits/cycle via LDDW instructions; L1 program memory: 256
bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit switching)]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
Low DSP activity model:
CPU: 2 instructions/cycle with 1 LDH instruction [L1 data memory: 16 bits/cycle; L1 program memory: 256 bits per 4 cycles; L2/EMIF
EDMA: None]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
The actual current draw is highly application dependent. For more details on core and I/O activity, refer to the TMS320C6713/12C/11C
Power Consumption Summary application report (literature number SPRA889).
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PARAMETRIC INFORMATION
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