SM320C6713-EP_1 Datasheet, PDF (38/131 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SM320C6713-EP
SM320C6713B-EP
SGUS049I – AUGUST 2003 – REVISED SEPTEMBER 2009
Table 5-5. Peripheral Pin Selection Matrix⁽¹⁾
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SELECTION BITS
BIT
NAME
BIT
VAL
HPI_EN
(boot config 0
pin)
MCASP0 ⁽²⁾ MCASP1
AHCLKX1
AHCLKR1
ACLKX1
ACLKR1
AFSX1
AFSR1
AMUTE1
AXR1[0]
to
AXR1[7]
HPI_EN
(boot config 1
pin)
None
0 None
ACLKX0
ACLKR0
MCBSP0DI
AFSX0
S (DEVCFG
bit)
1
AFSR0
AHCLKR
0
AXR0[0]
AXR0[1]
NO
AMUTE0
0 AXR0[5]
MCBSP1DI
S (DEVCFG
AXR0[6]
AXR0[7]
bit)
AMUTE0
1
AXR0[5]
AXR0[6]
AXR0[7]
TOUT0SEL
(DEVCFG
bit)
0
NO
AXR0[2]
1 AXR0[2]
TOUT1SEL
(DEVCFG
bit)
0
NO
AXR0[4]
1 AXR0[4]
0
HD12 (boot
config pin)
[13BGDP]⁽³⁾ ₁
I²C0
I²C1
None
All
PERIPHERAL PIN AVAILABILITY
MCBSP0 MCBSP1 TIMER0 TIMER1
All
None
All
None
TOUT0
NO
TOUT0
TOUT1
NO
TOUT1
HPI
GPIO
PINS
None
GP[0:1],
GP[3],
GP[8:15]
abc
Plus:
GP[2]
ctrl’d by
GP2EN bit
NO
All
GP[0:1],
GP[3],
GP[8:15]
EMIF
ED[7:0];
HD8 = 1/0
ED[7:0} side
[HD8 = 1 (Little)]
ED[31:24] side
[HD8 = 0 (Big)]
(1) Gray blocks indicate that the peripheral is not affected by the selection bit.
(2) The McASP0 pins, AXR0[3] and AHCLKX0, are shared with the timer input pins, TINP0 and TINP1, respectively. See Table 5-6 for
more detailed information.
(3) For more detailed information on endianness correction, see the EMIF Big Endian Mode Correctness [C6713B only] section of this data
sheet.
Table 5-6. C6713/13B Device Multiplexed/Shared Pins
MULTIPLEXED PIN
NAME
GDP
DEFAULT
FUNCTION
CLKOUT2/GP[2]
Y12 CLKOUT2
DEFAULT SETTING
DESCRIPTION
GP2EN = 0 (GPEN register bit)
When the CLKOUT2 pin is enabled, the CLK2EN bit in the
GP[2] function disabled, CLKOUT2 EMIF global control register (GBLCTL) controls the
enabled
CLKOUT2 pin.
CLK2EN = 0: CLKOUT2 held high
CLK2EN = 1: CLKOUT2 enabled to clock [default].
38
DEVICE CONFIGURATIONS
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