SM320C6713-EP_1 Datasheet, PDF (17/131 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SM320C6713-EP
SM320C6713B-EP
www.ti.com
3.3 Functional Block and CPU (DSP Core) Diagram
SGUS049I – AUGUST 2003 – REVISED SEPTEMBER 2009
32
EMIF
McASP1
McASP0
McBSP1
McBSP0
I2C1
I2C0
Timer 1
L2 Cache/
Memory
4 Banks
64K Bytes
Total
(up to
4-Way)
Enhanced
DMA
Controller
(16 channel)
L2
Memory
192K
Bytes
C6713/13B Digital Signal Processors
L1P Cache
Direct Mapped
4K Bytes Total
C67xä CPU
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path A
Data Path B
A Register File
B Register File
Control
Registers
Control
Logic
Test
In-Circuit
Emulation
(A) (A) (A)
.L1 .S1 .M1 .D1.
(A) (A) (A)
D2 .M2 .S2 .L2
Interrupt
Control
L1D Cache
2-Way
Set Associative
4K Bytes
Timer 0
Clock Generator and PLL
x4 through x25 Multiplier
/1 through /32 Dividers
Power-Down
Logic
GPIO
16
HPI
NOTE A: In addition to fixed-point instructions, these functional units execute floating-point instructions.
EMIF interfaces to:
-SDRAM
-SBSRAM
-SRAM
-ROM/flash and
I/O devices
McBSPs interface to:
-SPI control port
-High-speed TDM codecs
-AC97 codecs
-Serial EEPROM
McASPs interface to:
-I²S multichannel ADC, DAC, codec, DIR
-DIT: Multiple outputs
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DEVICE INFORMATION
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