SM320C6713-EP_1 Datasheet, PDF (70/131 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SM320C6713-EP
SM320C6713B-EP
SGUS049I – AUGUST 2003 – REVISED SEPTEMBER 2009
Table 8-4. PLL Control/Status Register (PLLCSR) (0x01B7 C100)
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31
28
27
24
23
20 19
16
Reserved
R-0
15
12
11
8
7
Reserved
R-0
Legend: R = Read only, R/W = Read/write, -n = value at reset
6
Stable
R–x
5
4
3
2
Reserved PLLRS Reserv
T
ed
R-0
RW−1 R/W−0
1
PLLPWRD
N
R/W−0b
0
PLLEN
RW−0
Table 8-5. PLL Control/Status Register (PLLCSR) Description
BIT NO.
31:7
6
5:4
3
2
1
0
NAME
Reserved
STABLE
Reserved
PLLRST
Reserved
PLLPWRDN
PLLEN
DESCRIPTION
Reserved. Read only, writes have no effect.
Clock input stable. This bit indicates if the clock input has stabilized.
0: Clock input not yet stable. Clock counter is not finished counting (default).
1: Clock input stable
Reserved. Read only, writes have no effect.
Asserts RESET to PLL
0: PLL reset released
1: PLL reset asserted (default)
Reserved. The user must write a 0 to this bit.
Select PLL power down
0: PLL operational (default)
1: PLL placed in power-down state
PLL mode enable
0: Bypass mode (default). PLL disabled Divider D0 and PLL are bypassed.
SYSCLK1/SYSCLK2/SYSCLK3 are divided down directly from input reference clock.
1: PLL enabled Divider D0 and PLL are not bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are
divided down from PLL output.
Table 8-6. PLL Multiplier (PLLM) Control Register (0x01B7 C110)
31
28
27
24
23
Reserved
R-0
15
12
11
8
7
Reserved
R-0
Legend: R = Read only, R/W = Read/write, -n = value at reset
20
19
16
5
4
0
PLLM
R/W−0 0111
70
PLL and PLL Controller
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