AFE8406 Datasheet, PDF (88/138 Pages) Texas Instruments – 14-Bit, 85 MSPS Dual ADC, 8-Channel Wideband Receiver

PRODUCT PREVIEW
AFE8406
SLWS168 - OCTOBER 2005
BIT15
BIT8
ragc_update_0(7:0)
0
0
0
0
0
0
0
0
BIT7
BIT0
integ_interval_0(23:16)
0
0
0
0
0
0
0
0
ragc_update_0(7:0) : Sets the number of receive AGC updates per sync event (0x00 is infinite).
integ_interval_0(23:16) : The eight MSBs of the integration time for receive AGC 0
Register name: RAGC0_CONFIG0
Page: 0x1840
Address: 0x6
BIT15
ragc_sync_delay_0(7:0)
0
0
0
0
0
0
0
BIT7
hp_corner_0(2:0)
acc_shift_0(4:0)
0
0
0
0
0
0
0
BIT8
0
BIT0
0
ragc_sync_delay_0(7:0) : The input sync to the receive AGC block is delayed by this number of samples.
hp_corner_0(2:0)
: Sets the corner frequency of the high pass filter. Larger values result in higher corner
frequencies
acc_shift_0(4:0)
: Selects the integrated power measurements result bits to be used as the error lookup table
address. A larger number means fewer samples will have to be integrated to achieve the same
result.
Register name: RAGC0_CONFIG1
Page: 0x1840
Address: 0x7
BIT15
acc_offset_0(5:0)
0
0
0
0
BIT7
err_shift_0(2:0)
0
0
0
0
BIT8
err_shift_0(4:3)
0
0
0
0
BIT0
delay_adj_0(4:0 )
0
0
0
0
acc_offset_0(5:0)
err_shift_0(4:0)
delay_adj_0(4:0)
: Constant subtracted from the integrated power measurement result before the error lookup table.
: Adjusts the loop gain by controlling the amount of shifting applied to the error lookup table output.
Larger values result in higher gain.
: Sets the delay difference, in samples, between the DVGA outputs and the value applied to the
sample multiplier.
Register name: RAGC0_SD_THRESH
Page: 0x1840
Address: 0x8
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
88
WWW.TI.COM