AFE8406 Datasheet, PDF (53/138 Pages) Texas Instruments – 14-Bit, 85 MSPS Dual ADC, 8-Channel Wideband Receiver

tristate(6:3)
PRODUCT PREVIEW
AFE8406
SLWS168 - OCTOBER 2005
Tristate controls for the rx_sync_out_X and rxout_X_X pins. Pins
are in tristate when the tristate register bits are set.
2.2.11.2 Parallel Output Interface
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
Output
format
rx_sync_out_6
rxclk_out
rxout_7_d
rxout_7_c
rxout_7_b
par_sync_out
rxclk_out
I(15)
I(14)
I(13)
rxout_4_b
rxout_4_a
rxout_3_d
rxout_3_c
rxout_3_b
I(1)
I(0)
Q(15)
Q(14)
Q(13)
Parallel I/Q
rxout_0_b
Q(1)
rxout_0_a
Q(0)
When a parallel I/Q interface is required, a 32 bit time division multiplexed output mode can be selected
using the rxout_X_X pins. This interface is provided for direct connection to the TMS320TCI110 Receive
Chip Rate ASSP when delayed antenna streams are not required. The output sample rate, rxclk_out clock
polarity, par_sync_out position and number of channels to be output are all programmable.
rxclk_out
par_sync_out
Parallel I/Q
IQ DDC0
IQ DDC1
IQ DDC2
IQ DDC3
IQ DDC4
IQ DDC5
The DDC channel serial interface synchronization source selections should all be programmed to the same
value when using this parallel output interface (each DDC channel ssel_serial(2:0) in the SYNC_0 register
should be programmed to the same rxsync_A/B/C/D value).
Decimation by 2 in the output interface can be achieved by setting the frame strobe interval and clock
divider to 1/2 the PFIR output rate. The parallel interface samples the PFIR outputs each time the transfer
interval defined by these two settings has completed.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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