AFE8406 Datasheet, PDF (59/138 Pages) Texas Instruments – 14-Bit, 85 MSPS Dual ADC, 8-Channel Wideband Receiver

PRODUCT PREVIEW
AFE8406
SLWS168 - OCTOBER 2005
3.3 Synchronization Signals
Various function blocks within the AFE8406 need to be synchronized in order to realize predictable results.
The AFE8406 provides a flexible system where each function block that requires synchronization can be
independently synchronized from either device pins or from a software “one-shot”. The one-shot option is
setup and triggered through control registers. The four sync input pins, rxsync_a, rxsync_b, rxsync_c and
rxsync_d are qualified on the rxclk rising clock edge.
The table below shows the different sync modes available:
Sync Select Code
000
001
010
011
100
101
110
111
Receive Sync Source
rxsync_a
rxsync_b
rxsync_c
rxsync_d
ddc sync counter terminal count
ddc sync triggered by s/w oneshot (register bit)
0 (always off)
1 (always on)
The tables below summarizes the blocks which have functions that can be synchronized using the above
eight sync source options:
Receive Common Syncs
Sync Name
sync_ddc_counter
sync_ddc
sync_rxsync_out
sync_adc_fifo
sync_tst_decim
sync_recv_pmeterX
sync_ragc_interval_X
sync_ragc_freeze_X
sync_ragc_clear_X
Purpose
Initializes the receive sync counter
Initializes the receive ADC interface & clock generation circuits
selects sync signal to be output on the rx_sync_out pin.
Initializes the input and output pointers in the ADC fifo circuits.
Initializes the testbus decimation counter.
Initializes the rxin power meters. {X = 0,1,2 or 3}
Initializes the rxin receive AGC timers. {X = 0,1,2 or 3}
rxin receive AGC freeze mode control. {X = 0,1,2 or 3}
Initializes the receive AGC error accumulator. {X = 0,1,2 or 3}
DDC Channel Syncs
Sync Name
sync_ddc_tadj
sync_ddc_tadj_reg
sync_ddc_nco
sync_ddc_freq
sync_ddc_phase
sync_ddc_dither
sync_ddc_cic
sync_ddc_pmeter
sync_ddc_gain
sync_ddc_agc
sync_ddc_agc_freeze
sync_ddc_serial
Purpose
Selects zero stuff moment in the tadj fine adjustment section.
Updates the tadj output pointer register delay in the tadj coarse adjustment section.
Resets the NCO accumulator.
Updates the NCO freq registers.
Updates the NCO phase register.
Initializes the NCO dither circuits.
Selects the CIC decimation moment.
Initializes the receive channel power meters.
Updates the DDC channel AGC gain registers
Initializes the AGC accumulator.
AGC freeze mode control.
Initializes the receive serial interface.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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