AFE8406 Datasheet, PDF (30/138 Pages) Texas Instruments – 14-Bit, 85 MSPS Dual ADC, 8-Channel Wideband Receiver

ssel_phase(2:0)
PRODUCT PREVIEW
Sync source for NCO phase register loading
AFE8406
SLWS168 - OCTOBER 2005
2.2.4 DDC Filtering and Decimation
The purpose of the receive filter chain is to isolate the signal of interest (and reject all other others) that has
been previously translated to baseband via the mixer and NCO. The overall decimation through the chain
needs to be considered. The goal, generally, is to output the isolated signal at a rate that is twice (2X) the
signal’s chip rate. For UMTS this would be 7.68 MSPS and for CDMA the output rate should be 2.4576
MSPS. TD-SCDMA systems require the output rate be the chip rate of 1.28 MSPS. The output interface
is programmed to decimate by 2 for the TD-SCDMA case.
Receive filtering and decimation is performed in several stages:
- Zero padding to interpolate the input sample rate (if needed) up to the rxclk rate
- High rate decimation (4 to 32) using a six stage cascade-integrate-comb filter (CIC)
- Decimate by two compensation filtering using the programmable compensating FIR filter (CFIR)
- Pulse-shape filtering via the programmable FIR filter (PFIR) with no decimation
- Output interface, serial or parallel format, with no decimation or decimate by 2
From
Mixer
Delay
Adjust
Zero Pad
Interp by {1,2,4,8}
Six Stage
CIC Filter
Dec by {4 - 32}
CFIR Filter
Dec by 2
PFIR Filter
no decimation
Output Interface
Dec by {1,2}
The table below contains some examples of decimation and sample rates at the output of each block for
UMTS, CDMA and TD -SCDMA standards at various supported input samples. For each example, the
differential ADC clocks are provided to the AFE8406 at the input sample rate and the rxclk is provided at
the zero pad output rate.
UMTS
UMTS
Input
Sample
Rate
(MSPS)
76.80
61.44
rxclk(MHz)
and Zero
Pad Output CIC
Zeros Rate
Deci-
Added (MSPS) mation
1
153.6
10
1
122.88
8
CIC
Output
Rate
(MSPS)
15.36
15.36
CFIR
Deci-
mation
2
2
CFIR
Output
Rate
(MSPS)
7.68
7.68
PFIR
Deci-
mation
1
1
PFIR
Output
Rate
(MSPS)
7.68
7.68
Output
Deci-
mation
1
1
CDMA
CDMA
CDMA
78.6432
0
78.6432
16
4.9152
2
78.6432
1 157.2864 32
4.9152
2
61.44
1
122.88
25
4.9152
2
2.4576
2.4576
2.4576
1
2.4576
1
1
2.4576
1
1
2.4576
1
TD-SCDMA 81.92
0
81.92
16
5.12
2
TD-SCDMA 76.80
0
76.80
15
5.12
2
TD-SCDMA 76.80
1
153.6
30
5.12
2
TD-SCDMA 61.44
1
122.88
24
5.12
2
2.56
2.56
2.56
2.56
1
2.56
2
1
2.56
2
1
2.56
2
1
2.56
2
Note: The DDC output interfaces, both serial and parallel formats, can be programmed to decimate by 2. For
the TD-SCDMA examples listed above, the DDC output rate is 1.28Msps (1x chip rate).
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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