AFE8406 Datasheet, PDF (68/138 Pages) Texas Instruments – 14-Bit, 85 MSPS Dual ADC, 8-Channel Wideband Receiver

PRODUCT PREVIEW
AFE8406
SLWS168 - OCTOBER 2005
Y(2:0) : Within each major block, there are up to 8 different Zones that can be addressed using the Y bits.
Y(2:0)
000
001
010
011
100
101
110
111
DDC Zone
PFIR coeffient lower 2 bits
PFIR coeffient upper 16 bits
CFIR coeffient lower 2 bits
CFIR coeffient upper 16 bits
Control registers
Not assigned
Not assigned
Not assigned
Receive Input Interface Zone
CHIPS control registers
RAGC control registers
Not assigned
Not assigned
Not assigned
Not assigned
Not assigned
Not assigned
Receive AGC RAMs Zone
RAGC0/2 ERRMAP
RAGC0/2 DVGAMAP
RAGC0/2 GAINMAP
Not assigned
RAGC1/3 ERRMAP
RAGC1/3 DVGAMAP
RAGC1/3 GAINMAP
Not assigned
Zp
: The Zp bit is the MSB of the address word sent to the registers and rams. This bit can be thought of as an
upper/lower selector of the 64 word addressing.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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