XIO2200A_12 Datasheet, PDF (83/203 Pages) Texas Instruments – PCI Express to PCI Bus Translation Bridge with 1394a OHCI and Two-Port PHY

Not Recommended for New Designs
Classic PCI Configuration Space
4.61 Control and Diagnostic Register 0
The contents of this register are used for monitoring status and controlling behavior of the bridge. See
Table 4−35 for a complete description of the register contents. It is recommended that all values within this
register be left at the default value. Improperly programming fields in this register may cause interoperability
or other problems.
PCI register offset:
Register type:
Default value:
C0h
Read/Write
0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RESET STATE 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−35. Control and Diagnostic Register 0 Description
BIT FIELD NAME ACCESS
DESCRIPTION
31:24† PRI_BUS_NUM
R
This field contains the captured primary bus number
23:19†
PRI_DEVICE_
NUM
R
This field contains the captured primary device number
18:16
RSVD
R
Reserved. Returns 000b when read.
15:14†
RSVD
RW
Reserved. Bits 15:14 default to 00b. If this register is programmed via EEPROM or another
mechanism, the value written into this field must be 00b.
13:12
RSVD
R
Reserved. Returns 00b when read.
11:8†
RSVD
RW
Reserved. Bits 11:8 default to 0000b. If this register is programmed via EEPROM or another
mechanism, the value written into this field must be 0000b.
7
RSVD
R
Reserved. Returns 0b when read.
Prefetch 4X enable. This bit sets the prefetch behavior for upstream memory read multiple
transactions. If bit 24 (FORCE_MRM) in the general control register (offset D4h, see Section 4.65)
is set, then all upstream memory read transactions will prefetch the indicated number of cache lines.
If bit 19 (READ_PREFETCH_DIS) in the general control register (offset D4h, see Section 4.65) is
6† PREFETCH_4X RW set, then this bit has no effect and only 1 DWORD will be fetched.
0 = The bridge will prefetch up to 2 cache lines, as defined in the cache line size register (offset
0Ch, see Section 4.6) for upstream memory read multiple (MRM) transactions (default)
1 = The bridge device will prefetch up to 4 cache lines, as defined in the cache line size register
(offset 0Ch, see Section 4.6) for upstream memory read multiple (MRM) transactions.
5:4†
UP_REQ_BUF
_VALUE
PCI upstream req-res buffer threshold value. The value in this field controls the buffer space that
must be available for the bridge to accept a PCI bus transaction. If the cache line size is not valid,
then the bridge will use 8 DW for calculating the threshold value
RW
00 = 1 Cacheline + 4 DW (default)
01 = 1 Cacheline + 8 DW
10 = 1 Cacheline + 12 DW
11 = 2 Cachelines + 4 DW
3†
UP_REQ_BUF
_CTRL
PCI upstream req-res buffer threshold control. This bit enables the PCI upstream req-res buffer
RW
threshold control mode of the bridge.
0 = PCI upstream req-res buffer threshold control mode disabled (default)
1 = PCI upstream req-res buffer threshold control mode enabled
2†
CFG_ACCESS
_MEM_REG
RW
Configuration access to memory-mapped registers. When this bit is set, the bridge allows
configuration access to memory-mapped configuration registers.
1†
RSVD
RW
Reserved. Bit 1 defaults to 0b. If this register is programmed via EEPROM or another mechanism,
the value written into this field must be 0b.
0
RSVD
R
Reserved. Returns 0b when read.
† _{These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.}
70 SCPS154C
March 5 2007 − June 2011