XIO2200A_12 Datasheet, PDF (126/203 Pages) Texas Instruments – PCI Express to PCI Bus Translation Bridge with 1394a OHCI and Two-Port PHY

Not Recommended for New Designs
1394 OHCI—PCI Configuration Space
7 1394 OHCI—PCI Configuration Space
The 1394 OHCI core is integrated as a PCI device behind the PCI-Express to PCI Bridge. The configuration
header for the 1394 OHCI portion of the design is compliant with the PCI Specification as a standard header.
Table 7−1 illustrates the configuration header that includes both the predefined portion of the configuration
space and the user definable registers.
Since the 1394 OHCI configuration space is accessed over the bridge secondary PCI bus, PCI Express type
1 configuration read and write transactions are required when accessing these registers. The 1394 OHCI
configuration register map is accessed as device number 0 and function number 0. Of course, the bus number
is determined by the value that is loaded into the Secondary Bus Number field at offset 19h within the PCI
Express configuration register map.
All bits marked with a † are reset by a PCI Express reset (PERST), a GRST, or the internally-generated
power-on reset. The remaining register bits are reset by a PCI Express hot reset, PERST, GRST, or the
internally-generated power-on reset.
Table 7−1. 1394 OHCI Configuration Register Map
BIST
Device ID
Status
Class code
Header type
REGISTER NAME
Latency timer
Vendor ID
Command
Revision ID
Cache line size
OFFSET
00h
04h
08h
0Ch
Subsystem ID†
Reserved
OHCI base address
TI extension base address
CIS base address
Reserved
CIS pointer
Subsystem vendor ID†
Reserved
PCI power management capabilities pointer
Reserved
10h
14h
18h
1Ch−27h
28h
2Ch
30h
34h
38h
Maximum latency† Minimum grant†
Interrupt pin
Interrupt line
PCI OHCI control
Power management capabilities
Next item pointer
Capability ID
PM data (RSVD)
PMCSR_BSE
Power management control and status†
Reserved
PCI PHY control†
Miscellaneous configuration†
3Ch
40h
44h
48h
4Ch−EBh
ECh
F0h
Link enhancement control†
F4h
Subsystem access†
F8h
TI proprietary
FCh
† _{One or more bits in this register are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.}
7.1 Vendor ID Register
The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the OHCI
controller. The vendor ID assigned to Texas Instruments is 104Ch.
PCI register offset:
Register type:
Default value:
00h
Read-only
104Ch
BIT NUMBER 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RESET STATE 0
0
0
1
0
0
0
0
0
1
0
0
1
1
0
0
March 5 2007 − June 2011
SCPS154C 113