XIO2200A_12 Datasheet, PDF (164/203 Pages) Texas Instruments – PCI Express to PCI Bus Translation Bridge with 1394a OHCI and Two-Port PHY

Not Recommended for New Designs
1394 OHCI Memory-Mapped Register Space
8.32 Node Identification Register
The node identification register contains the address of the node on which the OHCI-Lynx™ chip resides, and
indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15−6) and the
NodeNumber field (bits 5−0) is referred to as the node ID. See Table 8−24 for a complete description of the
register contents.
OHCI register offset:
Register type:
Default value:
E8h
Read/Write/Update, Read/Update, Read-only
0000 FFXXh
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RESET STATE 1 1 1 1 1 1 1 1 1 1 X X X X X X
BIT
31
30
29−28
27
26−16
15−6
5−0
FIELD NAME
iDValid
root
RSVD
CPS
RSVD
busNumber
NodeNumber
Table 8−24. Node Identification Register Description
TYPE
RU
DESCRIPTION
Bit 31 indicates whether or not the controller has a valid node number. It is cleared when a 1394 bus
reset is detected and set to 1b when the controller receives a new node number from its PHY layer.
RU
R
RU
R
RWU
Bit 30 is set to 1b during the bus reset process if the attached PHY layer is root.
Reserved. Bits 29 and 28 return 00b when read.
Bit 27 is set to 1b if the PHY layer is reporting that cable power status is OK.
Reserved. Bits 26−16 return 000 0000 0000b when read.
This field identifies the specific 1394 bus the controller belongs to when multiple 1394-compatible
buses are connected via a bridge. The default value for this field is all 1s.
RU This field is the physical node number established by the PHY layer during self-identification. It is
automatically set to the value received from the PHY layer after the self-identification phase. If the PHY
layer sets the nodeNumber to 63, then software must not set bit 15 (run) in the asynchronous context
control register (see Section 8.40) for either of the AT DMA contexts.
March 5 2007 − June 2011
SCPS154C 151