XIO2200A_12 Datasheet, PDF (188/203 Pages) Texas Instruments – PCI Express to PCI Bus Translation Bridge with 1394a OHCI and Two-Port PHY

Not Recommended for New Designs
1394 PHY Configuration Space
10.4 Vendor-Dependent Register
The vendor-dependent page provides access to the special control features of the controller, as well as to
configuration and status information used in manufacturing test and debug. This page is selected by writing
7 to the Page_Select field in base register 7. Table 10−7 shows the configuration of the vendor-dependent
page, and Table 10−8 shows the corresponding field descriptions.
ADDRESS
1000
1001
1010
1011
1100
1101
1110
1111
Table 10−7. Page 7 (Vendor-Dependent) Register Configuration
BIT POSITION
0
1
2
3
4
5
6
7
NPA
Reserved
Link_Speed
Reserved for test
Reserved for test
Reserved for test
Reserved for test
Reserved for test
Reserved for test
Reserved for test
Table 10−8. Page 7 (Vendor-Dependent) Register Field Descriptions
FIELD
NPA
SIZE
1
TYPE
RW
DESCRIPTION
Null-packet actions flag. This bit instructs the PHY layer to not clear fair and priority requests when a null packet
is received with arbitration acceleration enabled. If this bit is set to 1b, then fair and priority requests are cleared
only when a packet of more than 8 bits is received; ACK packets (exactly 8 data bits), null packets (no data bits),
and malformed packets (less than 8 data bits) do not clear fair and priority requests. If this bit is cleared to 0b,
then fair and priority requests are cleared when any non-ACK packet is received, including null packets or
malformed packets of less than 8 bits. This bit is cleared to 0b by system (hardware) reset and is unaffected by
bus reset.
Link_Speed 2
RW Link speed. This field indicates the top speed capability of the attached LLC. Encoding is as follows:
Code
Speed
00
S100
01
S200
10
S400
11
illegal
This field is replicated in the sp field of the self-ID packet to indicate the speed capability of the node (PHY and
LLC in combination). However, this field does not affect the PHY speed capability indicated to peer PHYs during
self-ID; the PHY layer identifies itself as S400 capable to its peers regardless of the value in this field. This field is
set to 10b (S400) by system (hardware) reset and is unaffected by bus reset.
10.5 Power-Class Programming
The PC0–PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field
(bits 21–23) of the transmitted self-ID packet. Table 10−9 shows the descriptions of the various power classes.
The default power-class value is loaded following a system (hardware) reset, but is overridden by any value
subsequently loaded into the Pwr_Class field in register 4.
Table 10−9. Power Class Descriptions
PC0–PC2
000
001
010
011
100
101
110
DESCRIPTION
Node does not need power and does not repeat power.
Node is self-powered and provides a minimum of 15 W to the bus.
Node is self-powered and provides a minimum of 30 W to the bus.
Node is self-powered and provides a minimum of 45 W to the bus.
Node may be powered from the bus and is using up to 3 W. No additional power is needed to enable the link.
Reserved
Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link.
111
Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link.
March 5 2007 − June 2011
SCPS154C 175