XIO2200A_12 Datasheet, PDF (134/203 Pages) Texas Instruments – PCI Express to PCI Bus Translation Bridge with 1394a OHCI and Two-Port PHY

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7.17 Capability ID and Next Item Pointer Registers
1394 OHCI—PCI Configuration Space
The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer
to the next capability item. See Table 7−13 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
44h
Read-only
0001h
BIT NUMBER 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RESET STATE 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
BIT
15−8
7−0
Table 7−13. Capability ID and Next Item Pointer Registers Description
FIELD NAME
NEXT_ITEM
TYPE
R
DESCRIPTION
Next item pointer. The OHCI controller supports only one additional capability that is communicated
to the system through the extended capabilities list; therefore, this field returns 00h when read.
CAPABILITY_ID
R Capability identification. This field returns 01h when read, which is the unique ID assigned by the PCI
SIG for PCI power-management capability.
7.18 Power Management Capabilities Register
The power management capabilities register indicates the capabilities of the OHCI core related to PCI power
management. See Table 7−14 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
46h
Read-only
7E02h
BIT NUMBER 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RESET STATE 0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
BIT
15−11
10
9
8−6
5
4
3
2−0
Table 7−14. Power Management Capabilities Register Description
FIELD NAME
PME_SUPPORT
D2_SUPPORT
D1_SUPPORT
AUX_CURRENT
DSI
RSVD
PME_CLK
TYPE
R
R
R
R
R
R
R
DESCRIPTION
PME support. This 5-bit field indicates the power states from which the OHCI core may assert PME.
This field returns a value of 01111b, indicating that PME is asserted from the D3_hot, D2, D1, and D0
power states.
D2 support. Bit 10 is hardwired to 1b, indicating that the OHCI controller supports the D2 power state.
D1 support. Bit 9 is hardwired to 1b, indicating that the OHCI controller supports the D1 power state.
Auxiliary current. This 3-bit field reports the 3.3-V_AUX auxiliary current requirements. This field returns
000b, because the 1394a core is not powered by V_AUX.
Device-specific initialization. This bit returns 0b when read, indicating that the OHCI controller does not
require special initialization beyond the standard PCI configuration header before a generic class driver
is able to use it.
Reserved. Bit 4 returns 0b when read.
PME clock. This bit returns 0b when read, indicating that no host bus clock is required for the OHCI
controller to generate PME.
PM_VERSION
R Power-management version. If bit 7 (PCI_PM_VERSION_CTRL) in the PCI miscellaneous
configuration register at offset F0h (see Section 7.22) is 0b, then this field returns 010b indicating
Revision 1.1 compatibility. If PCI_PM_VERSION_CTRL in the PCI miscellaneous configuration
register is 1b, then this field returns 011b indicating Revision 1.2 compatibility.
March 5 2007 − June 2011
SCPS154C 121