AM1808 Datasheet, PDF (81/264 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
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SPRS653 – FEBRUARY 2010
Table 6-6. AINTC System Interrupt Assignments
System Interrupt
0
1
2
3
4
5
6
7
8
9
10
11
Interrupt Name
COMMTX
COMMRX
NINT
PRU_EVTOUT0
PRU_EVTOUT1
PRU_EVTOUT2
PRU_EVTOUT3
PRU_EVTOUT4
PRU_EVTOUT5
PRU_EVTOUT6
PRU_EVTOUT7
EDMA3_0_CC0_INT0
12
EDMA3_0_CC0_ERRINT
13
EDMA3_0_TC0_ERRINT
14
EMIFA_INT
15
IIC0_INT
16
MMCSD0_INT0
17
MMCSD0_INT1
18
PSC0_ALLINT
19
RTC_IRQS[1:0]
20
SPI0_INT
21
T64P0_TINT12
22
T64P0_TINT34
23
T64P1_TINT12
24
T64P1_TINT34
25
UART0_INT
26
-
27
PROTERR
28
-
29
-
30
-
31
-
32
EDMA3_0_TC1_ERRINT
33
EMAC_C0RXTHRESH
34
EMAC_C0RX
35
EMAC_C0TX
36
EMAC_C0MISC
37
EMAC_C1RXTHRESH
38
EMAC_C1RX
39
EMAC_C1TX
40
EMAC_C1MISC
40
DDR2_MEMERR
42
GPIO_B0INT
43
GPIO_B1INT
44
GPIO_B2INT
45
GPIO_B3INT
Source
ARM
ARM
ARM
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
EDMA3_0 Channel Controller 0 Shadow Region 0 Transfer
Completion Interrupt
EDMA3_0 Channel Controller 0 Error Interrupt
EDMA3_0 Transfer Controller 0 Error Interrupt
EMIFA
I2C0
MMCSD0 MMC/SD Interrupt
MMCSD0 SDIO Interrupt
PSC0
RTC
SPI0
Timer64P0 Interrupt 12
Timer64P0 Interrupt 34
Timer64P1 Interrupt 12
Timer64P1 Interrupt 34
UART0
Reserved
SYSCFG Protection Shared Interrupt
Reserved
Reserved
Reserved
Reserved
EDMA3_0 Transfer Controller 1 Error Interrupt
EMAC - Core 0 Receive Threshold Interrupt
EMAC - Core 0 Receive Interrupt
EMAC - Core 0 Transmit Interrupt
EMAC - Core 0 Miscellaneous Interrupt
EMAC - Core 1 Receive Threshold Interrupt
EMAC - Core 1 Receive Interrupt
EMAC - Core 1 Transmit Interrupt
EMAC - Core 1 Miscellaneous Interrupt
DDR2 Controller
GPIO Bank 0 Interrupt
GPIO Bank 1 Interrupt
GPIO Bank 2 Interrupt
GPIO Bank 3 Interrupt
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Peripheral Information and Electrical Specifications
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