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AM1808 Datasheet, PDF (245/264 Pages) Texas Instruments – AM1808 ARM Microprocessor
AM1808
www.ti.com
SPRS653 – FEBRUARY 2010
6.32.1 GPIO Register Description(s)
BYTE ADDRESS
0x01E2 6000
0x01E2 6004
0x01E2 6008
0x01E2 6010
0x01E2 6014
0x01E2 6018
0x01E2 601C
0x01E2 6020
0x01E2 6024
0x01E2 6028
0x01E2 602C
0x01E2 6030
0x01E2 6034
0x01E2 6038
0x01E2 603C
0x01E2 6040
0x01E2 6044
0x01E2 6048
0x01E2 604C
0x01E2 6050
0x01E2 6054
0x01E2 6058
0x01E2 605C
0x01E2 6060
0x01E2 6064
0x01E2 6068
0x01E2 606C
0x01E2 6070
0x01E2 6074
0x01E2 6078
0x01E2 607C
0x01E2 6080
0x01E2 6084
Table 6-134. GPIO Registers
ACRONYM
REGISTER DESCRIPTION
REV
Peripheral Revision Register
RESERVED
Reserved
BINTEN
GPIO Interrupt Per-Bank Enable Register
GPIO Banks 0 and 1
DIR01
GPIO Banks 0 and 1 Direction Register
OUT_DATA01
GPIO Banks 0 and 1 Output Data Register
SET_DATA01
GPIO Banks 0 and 1 Set Data Register
CLR_DATA01
GPIO Banks 0 and 1 Clear Data Register
IN_DATA01
GPIO Banks 0 and 1 Input Data Register
SET_RIS_TRIG01 GPIO Banks 0 and 1 Set Rising Edge Interrupt Register
CLR_RIS_TRIG01 GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register
SET_FAL_TRIG01 GPIO Banks 0 and 1 Set Falling Edge Interrupt Register
CLR_FAL_TRIG01 GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register
INTSTAT01
GPIO Banks 0 and 1 Interrupt Status Register
GPIO Banks 2 and 3
DIR23
GPIO Banks 2 and 3 Direction Register
OUT_DATA23
GPIO Banks 2 and 3 Output Data Register
SET_DATA23
GPIO Banks 2 and 3 Set Data Register
CLR_DATA23
GPIO Banks 2 and 3 Clear Data Register
IN_DATA23
GPIO Banks 2 and 3 Input Data Register
SET_RIS_TRIG23 GPIO Banks 2 and 3 Set Rising Edge Interrupt Register
CLR_RIS_TRIG23 GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register
SET_FAL_TRIG23 GPIO Banks 2 and 3 Set Falling Edge Interrupt Register
CLR_FAL_TRIG23 GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register
INTSTAT23
GPIO Banks 2 and 3 Interrupt Status Register
GPIO Banks 4 and 5
DIR45
GPIO Banks 4 and 5 Direction Register
OUT_DATA45
GPIO Banks 4 and 5 Output Data Register
SET_DATA45
GPIO Banks 4 and 5 Set Data Register
CLR_DATA45
GPIO Banks 4 and 5 Clear Data Register
IN_DATA45
GPIO Banks 4 and 5 Input Data Register
SET_RIS_TRIG45 GPIO Banks 4 and 5 Set Rising Edge Interrupt Register
CLR_RIS_TRIG45 GPIO Banks 4 and 5 Clear Rising Edge Interrupt Register
SET_FAL_TRIG45 GPIO Banks 4 and 5 Set Falling Edge Interrupt Register
CLR_FAL_TRIG45 GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register
INTSTAT45
GPIO Banks 4 and 5 Interrupt Status Register
Copyright © 2010, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 245
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