AM1808 Datasheet, PDF (188/264 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
SPRS653 – FEBRUARY 2010
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Table 6-94. Ethernet Media Access Controller (EMAC) Registers (continued)
BYTE ADDRESS
0x01E2 3140
0x01E2 3144
0x01E2 3148
0x01E2 314C
0x01E2 3150
0x01E2 3154
0x01E2 3158
0x01E2 315C
0x01E2 3160
0x01E2 3164
0x01E2 3168
0x01E2 316C
0x01E2 3170
0x01E2 3174
0x01E2 31D0
0x01E2 31D4
0x01E2 31D8
0x01E2 31DC
0x01E2 31E0
0x01E2 31E4
0x01E2 31E8
0x01E2 31EC
0x01E2 3200 - 0x01E2 32FC
0x01E2 3500
0x01E2 3504
0x01E2 3508
0x01E2 3600
0x01E2 3604
0x01E2 3608
0x01E2 360C
0x01E2 3610
0x01E2 3614
0x01E2 3618
0x01E2 361C
0x01E2 3620
0x01E2 3624
0x01E2 3628
0x01E2 362C
0x01E2 3630
0x01E2 3634
0x01E2 3638
0x01E2 363C
0x01E2 3640
0x01E2 3644
0x01E2 3648
0x01E2 364C
0x01E2 3650
ACRONYM
RX0FREEBUFFER
RX1FREEBUFFER
RX2FREEBUFFER
RX3FREEBUFFER
RX4FREEBUFFER
RX5FREEBUFFER
RX6FREEBUFFER
RX7FREEBUFFER
MACCONTROL
MACSTATUS
EMCONTROL
FIFOCONTROL
MACCONFIG
SOFTRESET
MACSRCADDRLO
MACSRCADDRHI
MACHASH1
MACHASH2
BOFFTEST
TPACETEST
RXPAUSE
TXPAUSE
(see Table 6-95)
MACADDRLO
MACADDRHI
MACINDEX
TX0HDP
TX1HDP
TX2HDP
TX3HDP
TX4HDP
TX5HDP
TX6HDP
TX7HDP
RX0HDP
RX1HDP
RX2HDP
RX3HDP
RX4HDP
RX5HDP
RX6HDP
RX7HDP
TX0CP
TX1CP
TX2CP
TX3CP
TX4CP
REGISTER DESCRIPTION
Receive Channel 0 Free Buffer Count Register
Receive Channel 1 Free Buffer Count Register
Receive Channel 2 Free Buffer Count Register
Receive Channel 3 Free Buffer Count Register
Receive Channel 4 Free Buffer Count Register
Receive Channel 5 Free Buffer Count Register
Receive Channel 6 Free Buffer Count Register
Receive Channel 7 Free Buffer Count Register
MAC Control Register
MAC Status Register
Emulation Control Register
FIFO Control Register
MAC Configuration Register
Soft Reset Register
MAC Source Address Low Bytes Register
MAC Source Address High Bytes Register
MAC Hash Address Register 1
MAC Hash Address Register 2
Back Off Test Register
Transmit Pacing Algorithm Test Register
Receive Pause Timer Register
Transmit Pause Timer Register
EMAC Statistics Registers
MAC Address Low Bytes Register, Used in Receive Address Matching
MAC Address High Bytes Register, Used in Receive Address Matching
MAC Index Register
Transmit Channel 0 DMA Head Descriptor Pointer Register
Transmit Channel 1 DMA Head Descriptor Pointer Register
Transmit Channel 2 DMA Head Descriptor Pointer Register
Transmit Channel 3 DMA Head Descriptor Pointer Register
Transmit Channel 4 DMA Head Descriptor Pointer Register
Transmit Channel 5 DMA Head Descriptor Pointer Register
Transmit Channel 6 DMA Head Descriptor Pointer Register
Transmit Channel 7 DMA Head Descriptor Pointer Register
Receive Channel 0 DMA Head Descriptor Pointer Register
Receive Channel 1 DMA Head Descriptor Pointer Register
Receive Channel 2 DMA Head Descriptor Pointer Register
Receive Channel 3 DMA Head Descriptor Pointer Register
Receive Channel 4 DMA Head Descriptor Pointer Register
Receive Channel 5 DMA Head Descriptor Pointer Register
Receive Channel 6 DMA Head Descriptor Pointer Register
Receive Channel 7 DMA Head Descriptor Pointer Register
Transmit Channel 0 Completion Pointer Register
Transmit Channel 1 Completion Pointer Register
Transmit Channel 2 Completion Pointer Register
Transmit Channel 3 Completion Pointer Register
Transmit Channel 4 Completion Pointer Register
188 Peripheral Information and Electrical Specifications
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