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TLC34058-110M Datasheet, PDF (8/21 Pages) Texas Instruments – 256 x 24 COLOR PALETTE
TLC34058-110M
256 × 24 COLOR PALETTE
SGLS075 – JANUARY 1994
operating characteristics over recommended ranges of supply voltage and operating free-air
temperature, Rset = 523 Ω, Vref = 1.235 V (unless otherwise noted)
analog outputs
EL
Integral linearity error (each DAC)
ED Differential linearity error
Gray-scale error
IO
Output current
LSB size
DAC to DAC matching
Output compliance voltage
† All typical values are at TA = 25°C.
PARAMETER
White level relative to blank
White level relative to black
Black level relative to blank
Blank level on IOR, IOB
Blank level on IOG
Sync level on IOG
MIN TYP†
17.69
16.74
0.95
– 10
6.29
– 10
–1
19.05
17.62
1.44
5
7.6
5
69.1
2%
MAX
±1
±1
± 5%
20.4
18.5
1.9
50
8.96
50
5%
1.2
UNIT
LSB
LSB
mA
µA
mA
µA
µA
V
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, Rset = 523 Ω, Vref = 1.235 V (see Note 2)
PARAMETER
MIN TYP MAX UNIT
ten1 CE low to data bus enabled
ten2 CE low to data valid
tdis CE high to data bus disabled
td
Analog output delay time (see Note 3)
tt
Analog output transition time (see Note 4)
ts
Analog output settling time (see Note 5)
Glitch impulse (see Note 6)
10
ns
75 ns
15 ns
10
ns
2
ns
9
ns
50
pV-s
Analog output skew
0
ns
2
Pipeline delay
clock
6
10 cycles
NOTES: 2. TTL input signals are 0 to 3 V with less than 3 ns rise/fall times between 10% and 90% levels. ECL input signals are VDD – 1.8 V
to VDD – 0.8 V with less than 2 ns rise/fall times between 20% and 80% levels. For input and output signals, timing reference points
are at the 50% signal level. Analog output loads are less than 10 pF. D0 – D7 output loads are less than 40 pF.
3. Measured from 50% point of rising clock edge to 50% point of full-scale transition
4. Measured between 10% and 90% of full-scale transition
5. Measured from 50% point of full-scale transition to output settling within ± 1 LSB. Settling time does not include clock and data
feedthrough.
6. Glitch impulse includes clock and data feedthrough. The – 3-dB test bandwidth is twice the clock rate.
8
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