TLC34058-110M Datasheet, PDF (7/21 Pages) Texas Instruments – 256 x 24 COLOR PALETTE

TLC34058-110M
256 × 24 COLOR PALETTE
SGLS075 – JANUARY 1994
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature, R_set = 523 Ω, V_ref = 1.235 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP† MAX UNIT
Iref
kSVR
Input reference current
Supply voltage rejection ratio
f = 1 kHZ,
See Figure 4
C8 = 0.1 µF,
10
µA
0.5
%
%∆VDD
IDD
Supply current
IIH
High-level input current
IIL
Low-level input current
CLK, CLK
Other inputs
CLK, CLK
Other inputs
VDD = 5 V,
VDD = 5.5 V,
VI = VCC
VI = 2.4 V
VI = 0 V
VI = 0.8 V
TA = 20°C
TA = – 55°C
195
mA
550
10 µA
10 µA
– 10 µA
– 10 µA
Ci
Input capacitance, digital
f = 1 MHz,
VI(PP) = 1 V
4 20* pF
Ci(CLK) Input capacitance, CLK, CLK
VOH High-level output voltage, D0 – D7
f = 1 MHz,
VI(PP) = 1 V
IOH = – 800 µA
2.4
4 20* pF
V
VOL
IOZ
Low-level output voltage, D0 – D7
High-impedance-state output current
IOL = 6.4 mA
0.4 V
10 µA
zo
Output impedance
50
kΩ
Co
Output capacitance (f = 1 MHz, IO = 0)
13 20* pF
* On products compliant to MIL-STD-883, Class B, this parameter is not production tested.
† _{All typical values are at TA = 25°C.}
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, R_set = 523 Ω, V_ref = 1.235 V (see Note 2)
MIN MAX UNIT
Clock frequency
110 MHz
LD frequency
27.5 MHz
tsu1 Setup time, R/W, C0, C1 high before CE↓
tsu2 Setup time, write data before CE↑
tsu3 Setup time, pixel and control
0
ns
35
ns
3
ns
th1 Hold time, R/W, C0, C1 high after CE↓
15
ns
th2 Hold time, write data after CE↑
3
ns
th3 Hold time, pixel and control
2
ns
tw1 Pulse duration, CE low
50
ns
tw2 Pulse duration, CE high
25
ns
tw3 Pulse duration, CLK high
4
ns
tw4 Pulse duration, CLK low
4
ns
tw5 Pulse duration, LD high
tw6 Pulse duration, LD low
15
ns
15
ns
tc1 Clock cycle time
9.09
ns
tc2 LD cycle time
36.36
ns
† _{See Figures 1 and 2.}
NOTE 2: TTL input signals are 0 to 3 V with less than 3 ns rise/fall times between 10% and 90% levels. ECL input signals are VDD – 1.8 V to
VDD – 0.8 V with less than 2 ns rise/fall times between 20% and 80% levels. For input and output signals, timing reference points are
at the 50% signal level. Analog output loads are less than 10 pF. D0 – D7 output loads are less than 40 pF.
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