TLC34058-110M Datasheet, PDF (19/21 Pages) Texas Instruments – 256 x 24 COLOR PALETTE

PRINCIPLES OF OPERATION
TLC34058-110M
256 × 24 COLOR PALETTE
SGLS075 – JANUARY 1994
Table 7. Command Register
COMMAND-
REGISTER
BIT
COMMAND-REGISTER
BIT FUNCTION
COMMAND-REGISTER BIT DESCRIPTION
CR7
Multiplex-select bit
low: selects 4:1 multiplexing
high: selects 5:1 multiplexing
This bit selects either 4:1 or 5:1 multiplexing for the palette RAM and overlay-register address,
SYNC, and BLK inputs. If 4:1 multiplexing is selected, the device ignores the E palette RAM and
overlay-register-address inputs. These inputs should be connected to GND, and the LD signal
frequency should be 1/4 of the clock frequency. If 5:1 is specified, all of the palette RAM and
overlay-register-address inputs are used and the LD signal should be 1/5 of the clock frequency.
CR6
CR5, CR4
CR3
CR2
CR1
CR0
RAM-enable bit
low: use overlay register 0
high: use palette RAM
Blink-rate-select bits
00: 16 on, 48 off (25/75)
01: 16 on, 16 off (50/50)
10: 32 on, 32 off (50/50)
OL1 blink-enable bit
low: disable blinking
high: enable blinking
OL0 blink-enable bit
low: disable blinking
high: enable blinking
OL1 display-enable bit
low: disable
high: enable
OL0 display-enable bit
low: disable
high: enable
When the overlay select bits (OL0 and OL1) are both low, this bit causes the DACs color
information to be selected from overlay register 0 or the palette RAM.
These two bits select the blink-rate cycle time and duty cycle. The on and off numbers specify
the blink-rate cycle time as the number of vertical periods. The numbers in parentheses specify
the duty cycle in (on/off) percent.
If this bit is a high, the OL1 (A – E) inputs toggle between a logic 0 and their input value at the
selected blink rate before latching the incoming pixel data. Simultaneously, command-register
CR1 must be set high. If the CR2 bit is low, the OL0 (A – E) inputs are unaffected.
If this bit is high, the OL0 (A – E) inputs toggle between a logic 0 and their input value at the
selected blink rate before latching the incoming pixel data. Simultaneously, command-register
CR0 must be set high. If the CR2 bit is low, the OL0 (A – E) inputs are unaffected.
If this bit is low, the OL1 (A – E) inputs are forced to a logic 0 before latching the incoming pixel
data. If the CR1 bit is high, the OL1 (A – E) inputs are affected.
If this bit is low, the OL0 (A – E) inputs are forced to a logic 0 before latching the incoming pixel
data. If the CR0 bit is high, the OL0 (A – E) inputs are affected.
read-mask register
The read-mask register is used to enable (high) or disable (low) the eight bit planes (P0 – P7) within the
palette-RAM addresses. The enabling or disabling is accomplished by logic ANDing the read-mask register with
the palette-RAM address before addressing the palette RAM. Read-mask register bit 0 corresponds to data-bus
line D0. The MPU can write to or read from this register at any time. This register is not initialized.
blink-mask register
The blink-mask register is used to enable (high) or disable (low) the blinking of bit planes within the palette-RAM
addresses. For example, if blink-mask register bit n is set high, the true Pn value addresses the palette RAM
during the on portion of the blink cycle. During the off part of the blink cycle, the Pn value is replaced with a 0
before the palette RAM is addressed. The blink-rate cycle time and duty cycle is specified by command-register
bits CR4 and CR5. If blink-mask-register bit n is set low, the true Pn value always addresses the palette RAM.
Blink-mask-register bit 0 corresponds to data-bus line D0. This register is not initialized.
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