TLC34058-110M Datasheet, PDF (16/21 Pages) Texas Instruments – 256 x 24 COLOR PALETTE

TLC34058-110M
256 × 24 COLOR PALETTE
SGLS075 – JANUARY 1994
PRINCIPLES OF OPERATION
control-register write/read
The four control registers are addressed with internal-address-register values 04 – 07. On writing to or reading
from the internal-address register, the additional address bits ADDRab are automatically reset to 0. To facilitate
read-modify-write operations, the internal-address register does not increment after writing to or reading from
the control registers. All control registers may be accessed at any time. When accessing the control registers,
C0 and C1 are respectively set low and high. Refer to Table 3 for a quick reference.
R/W
C1
L
L
L
H
H
L
H
H
X = irrelevant
Table 3. Writing to or Reading From Control Registers
C0 ADDRba ADDRab
FUNCTION
L
X
X
Write ADDR0 – ADDR7: D0 – D7 → ADDR0 – ADDR7; 0 → ADDRa,b
L
L
L
Write control register: D0 – D7 → control register
L
X
X
Read ADDR0 – ADDR7: ADDR0 – ADDR7 → D0 – D7; 0 → ADDRa,b
L
L
L
Read control register: control register → D0 – D7
summary of internal-address-register operations
Table 4 provides a summary of operations that use the internal-address register. Figure 1 presents the read/write
timing for the device. If an invalid address is loaded into the internal-address register, the device ignores
subsequent data from the MPU during a write operation and sends incorrect data to the MPU during a read
operation.
Table 4. Internal-Address-Register Operations
INTERNAL-ADDRESS-
REGISTER VALUE
C1
(ADDR0 – ADDR7) (HEX)
00 – FF
L
00 – 03
H
04
H
05
H
06
H
07
H
ADDRab
C0
MPU ACCESS
(COUNTS
MODULO 3)
00
H
Color-palette RAM
01
11
00
H
Over color 0 to 3
01
110
L
Read-mask register
L
Blink-mask register
L
Command register
L
Test register
COLOR
Red value
Green value
Blue value
Red value
Green value
Blue value
interruption of display-refresh pixel data (via simultaneous pixel-data retrieval and MPU write)
If the MPU is writing to a particular palette-RAM location or overlay register (during the blue cycle) and the
display-refresh process is accessing pixel data from the same RAM location or overlay register, one or more
pixels on the display screen may be disturbed. If the MPU write data is valid during the complete chip-enable
period, a maximum of one pixel is disturbed.
16
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443