TLC34058-110M Datasheet, PDF (5/21 Pages) Texas Instruments – 256 x 24 COLOR PALETTE

TLC34058-110M
256 × 24 COLOR PALETTE
SGLS075 – JANUARY 1994
Terminal Functions
TERMINAL
NAME
NO.† ^I/O
DESCRIPTION
BLK
69
I Composite blank control input. This TTL-compatible blanking input is stored in the input latch on the rising edge
of LD. When low, BLK drives the DAC outputs to the blanking level as shown in Table 6. This causes the P0 – P7
(A – E) and OL0 – OL1 (A – E) inputs to be ignored. When high, BLK allows the device to perform in the standard
manner.
C0, C1
34, 35
I Command control inputs. C0 and C1 specify the type of write or read operation (see Tables 1, 2, 3, and 4). These
TTL-compatible inputs are latched on the falling edge of CE.
CE
30
I Chip-enable input. This TTL-compatible input control allows data to be stored and enables data to be written
or read (see Figure 1). When low, CE enables data to be written or read. When high, CE allows data to be
internally latched on the rising edge during write operations. Care should be taken to avoid transients on this
input.
CLK
72
I _{Clock input. CLK provides the pixel clock rate. CLK and CLK inputs are designed to be driven by ECL logic using}
a 5-V single supply.
CLK
71
I Clock input. CLK is the complement of CLK and also provides the pixel clock rate.
COMP
D0 – D7
42
22 – 29
I Compensation input. COMP is used to compensate the internal reference amplifier (see the video generation
section). A 0.1-µF ceramic capacitor is connected between this terminal and VDD (see Figure 4). The highest
possible supply voltage rejection ratio is attained by connecting the capacitor to VDD rather than to GND.
I Data input bus. This TTL-compatible bus transfers data into or out of the device. The data bus is an 8-bit
bidirectional bus where D0 is the least significant bit.
FS ADJ
GND
41
31, 32,
44, 46,
75
I Full-scale adjust control input. A resistor Rset (see Figure 4), which is connected between this terminal and
GND, controls the magnitude of the full-scale video signal. The proportional current and voltage relationships
in Figure 3 are maintained independently of the full-scale output current. The relationships between Rset and
the IOR, IOG, and IOB full-scale output currents are:
Rset(Ω) = 11294 × Vref(V) / IOG(mA)
IOR, IOB (mA) = 8067 × Vref(V) / Rset(Ω)
Ground. All GND terminals must be connected together.
IOR, IOG
IOB
38, 39, O Current outputs red, green, and blue. High-impedance red, green, and blue video analog current outputs can
40
directly drive a 75-Ω cable coaxial terminated at each end (see Figure 4).
LD
70
I _{Load-control input. This TTL-compatible load control (LD) input latches the P0 – P7 (A – E), OL0 – OL1 (A – E),}
BLK, and SYNC inputs on its rising edge. The LD strobe occurs at 1/4 or 1/5 the clock rate and may be phased
independently of CLK and CLK. The LD duty cycle limits are specified in the timing requirements table.
OL0A – OL1A
OL0B – OL1B
OL0C – OL1C
OL0D – OL1D
OL0E – OL1E
12 –21
l Overlay selection inputs. These TTL-compatible inputs for the palette-overlay registers are stored in the input
latch on the rising edge of LD. These inputs (up to 2 bits per pixel) along with bit CR6 of the command register
(refer to the command register section and Table 5) specify whether the color information is selected from the
palette RAM or the overlay registers. If the color information is selected from the overlay registers, the
OL0 – OL1 (A – E) inputs address a particular overlay register. The OL0 – OL1 (A – D) or OL0 – OL1 (A – E) inputs
are simultaneously input to the device (see the description of bit CR7 in the command register section). The
OL0 – OL1 (A) inputs are processed first, then the OL0 – OL1 (B) inputs, and so on. When obtaining the color
information from the overlay registers, the P0 – P7 (A – E) inputs are ignored. Unused inputs should be
connected to GND.
P0A – P7A
P0B – P7B
P0C – P7C
P0D – P7D
P0E – P7E
1 – 11, l Address inputs. These TTL-compatible inputs for the palette RAM are stored in the input latch on the rising edge
48 – 67,
of LD. These address inputs (up to 8 bits per pixel) select one of 256 24-bit words in the palette RAM, which
76 – 84
is subsequently input to the red, green, and blue D/A converters as three 8-bit or 4-bit bytes. Four or five
addresses are simultaneously input to the P0 – P7 (A – D) or P0 – P7 (A – E) ports, respectively (see the
description of bit CR7 in the command register section). The word addressed by P0A – P7A is first sent to the
DACs, then the word addressed by P0B – P7B, and so on. Unused inputs should be connected to GND.
REF
43
I Reference voltage input. Voltage of 1.235 V is supplied at this input. An external voltage reference circuit,
shown in Figure 4, is suggested. Generating the reference voltage with a resistor network is not recommended
since low-frequency power supply noise directly couples into the DAC output signals. This input must be
decoupled by connecting a 0.1-µF ceramic capacitor between Vref and GND.
† _{Terminal numbers shown are for the HFG package only. For the GA package terminal assignments, see page 3.}
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