THS8135 Datasheet, PDF (8/23 Pages) Texas Instruments – TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO (ITU-R.BT601) COMPLIANT FULL SCALE RANGE

THS8135
TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO
(ITU-R.BT601)—COMPLIANT FULL SCALE RANGE
SLAS343A – MAY 2001 – REVISED JUNE 2002
Table 4. THS8135 RGB/YCbCr Color Space and Input Formatter Configuration
M1_INT
L
L
H
H
M2_INT
L
H
L
H
CONFIGURATION
GBR 3x10b–4:4:4
YCbCr 3x10b–4:4:4
YCbCr 2x10b–4:2:2
YCbCr 1x10b–4:2:2
DESRIPTION
GBR mode 4:4:4. Data clocked in on each rising edge of CLK from G, B, and R input channels.
YCbCr mode 4:4:4. Data clocked in on each rising edge of CLK from Y, Cb, and Cr input channels.
YCbCr mode 4:2:2 2x10 bit. Data clocked in on each rising edge of CLK from Y channel. A sample
sequence of Cb-Cr should be applied to the Cr port. At the first rising edge of CLK after BLANK is
taken high, Cb should be present on this port.
YCbCr mode 4:2:2 1x10 bit (ITU-R.BT-656 compliant). Data clocked in on each rising edge of CLK
from Y channel. A sample sequence of Cb-Y-Cr-Y should be applied to the Y port. At the first rising
edge of CLK after BLANK is taken high, Cb should be present on this port.
selection of full- or reduced-scale ITU-R.BT601 modes (available in video DAC mode only)
In video DAC mode, BLNK_INT sets the blanking level generated on the DAC outputs as shown in Table 5. This
allows imposing a blanking level on the analog outputs corresponding to either full-scale code range or a
reduced-scale code range compliant to ITU-R.BT601. The blanking level is correctly positioned for either RGB
or YCbCr configurations, determined from the M1/M2 setting.
For generic DAC mode, BLNK_INT control is not available and the device always generates an output level
during BLANK low assuming full-scale input code range.
Table 5. Full-Scale or ITU.BT601 Reduced-Scale Mode Selection and
Impact on Blanking Level Positioning
M1_INT M2_INT BLNK_INT
L
L
L
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
H
H
L
H
H
H
AVAILABLE IN
VIDEO DAC (V)
AND
GENERIC DAC
(G) MODES?
V, G
V
V, G
V
V
V, G
V
V, G
OPERATION MODE
GBR 3x10b 4:4:4, full scale range
GBR 3x10b 4:4:4, ITU–R.BT601-compliant range
YCbCr 3x10b 4:4:4, full scale range
YCbCr 3x10b 4:4:4, ITU–R.BT601-compliant range
YCbCr 2x10b 4:2:2, ITU–R.BT601-compliant range
YCbCr 2x10b 4:2:2, full scale range
YCbCr 1x10b 4:2:2, ITU–R.BT601-compliant range
YCbCr 1x10b 4:2:2, full scale range
CHANNEL OUTPUT LEVEL
DURING BLANK ACTIVE
CORRESPONDING TO DAC
INPUT CODE:
AGY ABPb ARPr
0
0
0
64
64
64
0
512
512
64
512
512
64
512
512
0
512
512
64
512
512
0
512
512
In full-scale range, the DAC is driven with input codes 0-1023 to the desired video level, set by the resistor
connected to the FSADJ terminal (e.g., a full-scale video amplitude of 700 mV when terminated into 37.5 Ω and
when using the nominal R_FS value).
In reduced-scale ITU-R.BT601 range, it is the intention that full-scale video amplitude is reached when the
device is driven with digital inputs within the input code range shown in Table 6. Note that the code range is
unequal between RGBY on one hand and CbCr on the other hand. Figure 1 through Figure 4 illustrates the
difference between ITU-R.BT601 reduced-scale and full-scale code range operation. In reduced-range
configuration, the B/Cb and R/Cr components are digitally amplitude scaled internally. Note that there is no
scaling on the G/Y component. Therefore, to accommodate the 700-mV video compliance on all components,
the DAC full-scale output current needs to be increased between full-scale and reduced scale modes by a factor
of 1023/(940-64) by decreasing R_FS in that proportion.
This implementation has the advantage of avoiding amplitude scaling on the most critical G/Y component, while
still providing the possibility for instantaneous overshoot/undershoot on the analog component video output
when illegal signals according to ITU-R.BT601, such as super-black or super-white, are applied to the device.
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