THS8135 Datasheet, PDF (4/23 Pages) Texas Instruments – TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO (ITU-R.BT601) COMPLIANT FULL SCALE RANGE

THS8135
TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO
(ITU-R.BT601)—COMPLIANT FULL SCALE RANGE
SLAS343A – MAY 2001 – REVISED JUNE 2002
Terminal Functions
TERMINAL
NAME
NO.
ABPb
45
AGY
41
ARPr
43
AVDD
AVSS
BCb0–BCb9
40, 44
42, 46
10–1
BLANK
23
CLK
26
COMP
39
DVDD
12
DVSS
11
FSADJ
38
GY0–GY9
M1
36–27
47
M2
48
RCr0–RCr9
SYNC
13–22
24
I/O
DESCRIPTION
O Analog blue or Pb current output, capable of directly driving a double terminated 75-Ω coaxial cable
O Analog green or Y current output, capable of directly driving a double terminated 75-Ω coaxial cable
O Analog red or Pr current output, capable of directly driving a double terminated 75-Ω coaxial cable
I Analog power supply (3.3 V). All AVDD pins must be connected.
I Analog ground
I Blue or Cb pixel data input. Signals with index 0 denote the least significant bits.
I Blanking control input, active low. A rising edge on CLK latches BLANK. When asserted, the ARPr, AGY, and
ABPb outputs are driven to the blanking level, irrespective of the value on the data inputs. SYNC takes
precedence over BLANK, so asserting SYNC (low) while BLANK is active (low) results in sync generation.
The amplitude of the DAC outputs during BLANK active are determined by the color space and input code
range configurations of the device. BLANK control is available in both video and generic DAC modes.
I Clock input. A rising edge on CLK latches RCr0–9, GY0–9, BCb0–9, BLANK, SYNC, and SYNC_T.
In video DAC mode, the M1 and M2 inputs are latched by a rising edge on CLK as well but only when additional
conditions are satisfied as explained in their terminal description.
In generic DAC mode, M1 and M2 are continuously interpreted i.e. independent of additional conditions, to
determine color space and input data formats. This allows easier configuration.
O Compensation terminal. A 0.1-µF capacitor must be connected between COMP and AVDD.
I Digital power supply (1.8 V)
I Digital ground
I Full-scale adjust control. The full-scale current drive on each of the output channels is determined by the value
of a resistor RFS connected between this terminal and AVSS. Figure 5 shows the relationship between
full-scale output voltage compliance and RFS for the nominal DAC termination of 37.5 Ω.
I Green or Y pixel data input. Signals with index 0 denote the least significant bits.
I Operation mode control 1.
In video DAC mode, the second rising edge on CLK after a transition on SYNC latches M1. The interpretation
is dependent on the polarity of the last SYNC transition:
SYNC L → H: latched as M1_INT
SYNC H → L: latched as BLNK_INT.
Together with M2_INT, M1_INT configures the device as shown in Table 2 for video DAC mode. BLNK_INT
determines if the device operates with the full- or reduced-scale input code range. Together with the color
space configuration, this sets the amplitude of the blanking level on the analog output(s) as shown in Table 5.
In generic DAC mode, M1 is continuously interpreted as M1_INT, BLNK_INT control is not available and the
device always assumes full-scale input code range for blank level positioning.
I Operation mode control 2.
In video DAC mode, the second rising edge on CLK after a transition on SYNC latches M2. The interpretation
is dependent on the polarity of the last SYNC transition:
SYNC L → H: latched as M2_INT
SYNC H → L: latched as INS3_INT
Together with M1_INT, M2_INT configures the device as shown in Table 3 for video DAC mode. When
INS3_INT is high, the device inserts sync on all DAC outputs; when low, sync is inserted only on the AGY
output.
In generic DAC mode, M2 is continuously interpreted as M2_INT, INS3_INT control is not applicable, since
sync insertion is not available in generic DAC mode.
I Red or Cr pixel data input. Signals with index 0 denote the least significant bits.
I Sync control input, active low. A rising edge on CLK latches SYNC. When asserted, only the AGY output
(when INS3_INT=L, see terminal M2) for sync-on-G/Y, or ARPr, AGY, and ABPb outputs (when INS3_INT=H,
see terminal M2) for sync-on-all, are driven to the sync level, irrespective of the values on the data or BLANK
inputs. Therefore, SYNC should remain low for the whole duration of sync, which is in the case of a tri-level
sync both the negative and positive portion. See Figure 10 for timing control. SYNC control is only available in
video DAC mode.
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