THS8135 Datasheet, PDF (17/23 Pages) Texas Instruments – TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO (ITU-R.BT601) COMPLIANT FULL SCALE RANGE

THS8135
TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO
(ITU-R.BT601)—COMPLIANT FULL SCALE RANGE
SLAS343A – MAY 2001 – REVISED JUNE 2002
electrical characteristics over recommended operating conditions with f_CLK = 240 MSPS and use
of internal reference voltage V_REF, with R_FS = R_FS(nom) (unless otherwise noted) (continued)
digital inputs—dc characteristics
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
IIH
IIL
IIL(CLK)
High-level input current
Low-level input current
Low-level input current, CLK and IIH(CLK)
High-level input current, CLK
AVDD = 3.3 V, DVDD = 1.8 V,
Digital inputs and CLK at 0 V for IIL;
Digital inputs and CLK at 2 V for IIH
1
–1
µA
–1
1
CI
Input capacitance
TA = 25_C
5
pF
ts
Data and control inputs setup time
2
ns
th
Data and control inputs hold time
500
ps
td(D)
Digital process delay from first registered
color component of pixel^†
RGB and YCbCr 4:4:4
YCbCr 4:2:2 2 x 10 bit
YCbCr 4:2:2 1 x 10 bit
7.5
9.5
CLK
periods
10.5
† _{This parameter is assured by design. The digital process delay is defined as the number of CLK cycles required for the first registered color}
component of a pixel, starting from the time of registering it on the input bus, to propagate through all processing and appear at the DAC output
drivers. The remaining delay through the IC is the analog delay td(A) of the analog output drivers.
analog (DAC) outputs
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
DAC resolution
10
Bits
Static, best-fit, sync-on–all, video mode, RGB full-scale
–1.1/ –2/
0.9 1.5
INL
Integral nonlinearity
Static, best-fit, sync-on-all, video mode,
RGB ITU.R–BT601
–1.2/
0.8
–2/
1.5 ^LSB
Static, best fit, generic mode, 1.3 V
–1.61/ –2/
0.94 1.5
Static, sync-on-all, video mode, RGB full-scale
±0.4
±1
DNL
Differential nonlinearity
Static, sync-on-all, video mode, RGB ITU.R–BT601
Static, generic mode, 1.3 V
±0.5
–0.32/
0.24
±1 _LSB
PSRR
Power supply ripple rejection
ratio of DAC output (full scale)
f = DC, See Note 2
38.5
dB
XTALK Crosstalk between channels
See Note 3
f = 1 MHz
f = 30 MHz
–63
dB
–39
Vrefo
RR
Voltage reference output
VREF output resistance
KIMBAL Imbalance between DACs
CLK = 80 MSPS, See Note 4
1.13 1.15 1.16 V
276.5 284 294 Ω
Video mode,
RGB full-scale
–2% 1.8% 2%
Video mode,
RGB ITU-R.BT601
–3% 2.8%
3%
VOC
DAC output compliance voltage
(video only)
See Note 5
Video mode,
RGB full-scale
0.7
Video mode, RGB
ITU-R.BT601
0.817
V
Generic mode
1.3
NOTES:
2. PSRR is measured with a 0.1 µF capacitor between the COMP and AVDD pin; with a 0.1–µF capacitor connected between the VREF
pin and AVSS. The ripple amplitude is within the range 100 mVp–p to 500 mVp–p with the DAC output set to full scale and a
double-terminated 75 Ω (= 37.5 Ω) load. PSRR is defined as 20 x log(ripple voltage at DAC output/ripple voltage at AVDD input).
Limits from characterization only.
3. Crosstalk spec applies to each possible pair of the three DAC outputs. Limits are from characterization only.
4. The imbalance between DACs applies to all possible pairs of the three DACs.
5. Values at RFS=RFS(nom) ; limits from characterization only.
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