THS8135 Datasheet, PDF (14/23 Pages) Texas Instruments – TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO (ITU-R.BT601) COMPLIANT FULL SCALE RANGE

THS8135
TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO
(ITU-R.BT601)—COMPLIANT FULL SCALE RANGE
SLAS343A – MAY 2001 – REVISED JUNE 2002
CLK T0
T1
T2
T3
T4
T5
T6
T7
T8
RCr(0) RCr(1) RCr(2) RCr(3) RCr(4) RCr(5) RCr(6) RCr(7) RCr(8)
GY(0) GY(1) GY(2) GY(3) GY(4) GY(5) GY(6) GY(7) GY(8)
BCb(0) BCb(1) BCb(2) BCb(3) BCb(4) BCb(5) BCb(6) BCb(7) BCb(8)
Data Path Latency = 7.5 CLK Cycles
RCr(0), GY(0), BCb(0) Registered
ARPr, AGY, ABPb Output
Corresponding to RCr(0), GY(0), BCb(0)
Figure 7. Input Format and Latency YCbCr 4:4:4 and GBR 4:4:4 Modes
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
BLANK
RCr[9:0]
First Registered Sample on RCr[9:0] after L ⇒ H on BLANK is Interpreted as Cb[9:0]
Cb(0)
Cr(0)
Cb(2)
Cr(2)
Cb(4)
Cr(4)
Cb(6)
Cr(6)
Cb(8)
Cr(8)
Cb(10) Cr(10)
GY[9:0]
Y(0)
Y(1)
Y(2)
Y(3)
Y(4)
Y(5)
Y(6)
Y(7)
Y(8)
Y(9)
Y(10)
Y(11)
BCb[9:0] ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cb(0), Y(0) Registered
Data Path Latency = 9.5 CLK Cycles
Cr(0), Y(1) Registered
ARPr, AGY, ABPb Output
Corresponding to Cr(0),Y(0), Cb(0)
Figure 8. Input Format and Latency YCbCr 4:2:2 2x10-Bit Mode
CLK T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
BLANK
First Registered Sample on GY[9:0] after L ⇒ H on BLANK is Interpreted as Cb[9:0]
RCr[9:0_ÎÎ] _{ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ}
GY[9:0]
Cb(0)
Y(0)
Cr(0)
Y(2)
Cb(4)
Y(4)
Cr(4)
Y(6)
Cb(8)
Y(8)
Cr(8)
Y(10)
BCb[9:0^ÎÎ] ^{ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ}
Data Path Latency = 10.5 CLK Cycles
Cb(0) Registered Cr(0) Registered
Y(0) Registered
ARPr, AGY, ABPb Output
Corresponding to Cr(0),Y(0), Cb(0)
Figure 9. Input Format and Latency YCbCr 4:2:2 1x10-Bit Mode
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