THS8135 Datasheet, PDF (6/23 Pages) Texas Instruments – TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO (ITU-R.BT601) COMPLIANT FULL SCALE RANGE

THS8135
TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO
(ITU-R.BT601)—COMPLIANT FULL SCALE RANGE
SLAS343A – MAY 2001 – REVISED JUNE 2002
generic DAC mode versus video DAC mode (continued)
Because of the eliminated dc bias, the DAC output compliance for full-range video input can be higher in generic
DAC mode: up to 1.286 Vpp at nominal double 75-Ω termination load. This is high enough for the D/A conversion
of composite video (NTSC/PAL/SECAM), where the signal fed to the device contains the complete digital
composite waveform, including sync and color-burst.
Selection between generic DAC versus video DAC mode is controlled through a combination of SYNC and
SYNC_T settings. Since in video DAC mode, SYNC_T only determines the sync polarity, this signal has don’t
care status when no sync insertion takes place i.e., when SYNC is high. The THS8135 uses the logic level on
the SYNC_T input when SYNC is high to enter generic DAC mode: SYNC_T and SYNC are high → generic
DAC mode. Therefore, the user must make sure to keep SYNC_T low outside the sync insertion period (when
SYNC is high) to prevent entering generic DAC mode, when he intends to use the device in video DAC mode.
Table 1 shows how to select between video DAC and generic DAC mode.
Table 1. Video vs Generic Mode Selection
SYNC
1
1
1
1
0
0
BLANK
1
0
1
0
X
X
SYNC_T
1
1
0
0
0
1
OPERATION MODE AND DAC OUTPUT
Generic DAC mode. Blanking override inactive.
Generic DAC mode. Blanking override active. Blanking level position is according to the codes of Table 5,
however no dc bias is present on the Y, R, G, and B outputs
Video DAC mode. Blanking override inactive
Video DAC mode. Blanking override active. Blanking level position is according to the codes of Table 5, with dc
bias present on the Y, R, G, and B outputs as shown in Figure 1 and Figure 3.
Video DAC mode. Negative sync inserted
Video DAC mode. Positive sync inserted
device configuration using M1 and M2 in video DAC mode
In the video DAC mode, the configuration signals M1 and M2 are both sampled on the second rising edge of
the CLK input signal after a L → H or H → L transition on SYNC. Depending on the polarity of this last transition
on SYNC, M1 and M2 are interpreted differently by the THS8135, as shown in Table 2.
NOTE:
In the THS8133, only M2 is a sampled signal while M1 is continuously interpreted. By doing so here,
the additional input control signal BLNK_INT is generated. See the backward compatibility with the
THS8133 section.
If last event on
SYNC is:
H→L
L →H
Table 2. Interpretation of M1 in Video DAC Mode
Then M1 is interpreted on
the second CLK rising edge
following this event as:
BLNK_INT
M1_INT
DESCRIPTION
Sets operation with full or video (ITU–R.BT601) – input code range i.e., the full-scale
range is reached from either the 0–1023 10-bit input code range or the input code range of
Table 6, see also Table 5 for blanking level positions.
Sets device operation mode. See Table 4 and Table 5.
If last event on
SYNC is:
H →L
L →H
Table 3. Interpretation of M2 in VIdeo DAC Mode
Then M2 is interpreted on
the second CLK rising edge
following this event as:
INS3_INT
M2_INT
DESCRIPTION
Sets sync Insertion mode: SYNC low enables sync generation on one (INS3_INT=L) or all
three (INS3_INT=H) DAC outputs. SYNC_T determines the sync polarity.
Sets device operation mode. See Table 4 and Table 5.
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