THS8135 Datasheet, PDF (7/23 Pages) Texas Instruments – TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO (ITU-R.BT601) COMPLIANT FULL SCALE RANGE

THS8135
TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO
(ITU-R.BT601)—COMPLIANT FULL SCALE RANGE
SLAS343A – MAY 2001 – REVISED JUNE 2002
device configuration using M1 and M2 in generic DAC mode
To simplify device configuration in the generic DAC mode, the M1 and M2 configuration pins are continuously
interpreted as M1_INT and M2_INT respectively, i.e., their interpretation is not dependent on the last event on
SYNC and is not only sampled on the second rising CLK edge after a transition on SYNC. BLNK_INT and
INS3_INT controls are not available in generic mode. As a result, in generic DAC mode, the device always
operates with full-scale input range and no sync insertion is available.
M1_INT and M2_INT can be tied high or low externally to determine the input formatter setting and color space
for blank level positions. Blanking override is still available in generic DAC mode using the BLANK input. Generic
DAC mode only disables the dc bias for R, G, B, and Y component outputs.
Table 1 shows all combinations of these control signals. Note that when SYNC is low, it takes precedence over
BLANK.
selection of color space and input formatter configuration (available in video DAC and generic DAC modes)
Input data to the device can be supplied from a 3x10b GBR or YCbCr input port. If the device is configured to
take data from all three channels, the data is clocked in at each rising edge of CLK. All three DACs operate at
the full clock speed of CLK.
In the case of 4:2:2 sampled data (for YCbCr data), the device can be fed over either a 2x10 bit or 1x10 bit
multiplexed input port. An internal demultiplexer routes the input samples to the appropriate DAC: Y at the rate
of CLK, Cb and Cr each at rate of 1/2 CLK.
According to ITU-R.BT-656, the sample sequence is Cb-Y-Cr-Y over a 1x10-bit interface (Y-port). The sample
sequence starts at the first rising edge of CLK after BLANK has been taken high (inactive). Note that in this case
the frequency of CLK is 2x the Y conversion speed and 4x the conversion speed of both Cr and Cb.
In the case of a 2x10 bit input interface, both the Y-port and the Cr-port are sampled on every CLK rising edge.
The Cr-port carries the sample sequence Cb-Cr. The sample sequence starts at the first rising edge of CLK after
BLANK has been taken high (inactive). Note that in this case the frequency of CLK is equal to the conversion
speed of Y and 2x the conversion speed of both Cr and Cb.
Table 4 shows the possible configurations of the input formatter, as determined by the internal M1_INT and
M2_INT signals. The color space selection also determines the position of the blanking level and is explained
in the next section.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
7