SLK2701 Datasheet, PDF (8/21 Pages) Texas Instruments – OC-48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER

SLK2701
OCĆ48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER
SLLS518 − DECEMBER 2001
detailed description (continued)
The PECL output also provides preemphasis for compensating ac loss when driving a cable or PCB backplane
over long distance. The level of the preemphasis is programmable via the PRE1 and PRE2 pins. Users can use
software to control the strength of the preemphasis to optimize the device for a specific system requirement.
Table 4. Programmable De-emphasis
PRE1
PRE2
DE-EMPHASIS LEVEL
(Vodp/Vodd†−1)
0
0
De-emphasis disabled
1
0
10%
0
1
20%
1
1
30%
† _{Vodp: Differential voltage swing when there is a transition in the data stream.}
Vodd: Differential voltage swing when there is no transition in the data stream.
V(ODp)
V(ODd)
0
V(ODd)
Bit
Time
Bit
Time
V(ODp)
Figure 1. Output Differential Voltage Under De-emphasis
LVDS parallel data interface
The parallel data interface consists of a 4-bit parallel LVDS data and clock. The device conforms to the
OIF99.102 specification when operating at the OC-48 rate. When operating at lower serial rates, the clock and
data frequency are scaled down accordingly, as indicated in Table 1. The parallel data TXDATA[0:3] is latched
on the rising edge of TXCLK and then is sent to a data FIFO to resolve any phase difference between TXCLK
and REFCLK. If there is a FIFO overflow condition, the SPILL pin is set high. The FIFO resets itself to realign
between two clocks. The internal PLL for the clock synthesizer is locked to the REFCLK, and it is used as the
timing to serialize the parallel data (except for the loop timing mode where the recovered clock is used). On the
receive side, RXDATA[0:3] is updated on the rising edge of RXCLK. Figures 7 and 8 show the timing diagram
for the parallel interface.
The SLK2701 device also has a built-in parity checker and generator for error detection of the LVDS interface.
On the transmit side, it accepts the parity bit, TXPARP/N, and performs the parity checking function for even
parity. If an error is detected, it pulses the PAR_VALID pin low for two clock cycles. On the receive side, the parity
bit, RXPARP/N, is generated for the downstream device for parity error checking.
Differential termination 100-Ω resistors are included on-chip between TXDATAP/N and TXCLKP/N.
reference clock
The device accepts a 622.08-MHz clock. The REFCLK input is compatible with the LVDS level and also the
3.3-V LVPECL level using ac-coupling. A 100-Ω differential termination resistor is included on-chip, as well as
a dc-biasing circuit (3 kΩ to VDD and 4.5 kΩ to GND) for the ac-coupled case. A high quality REFCLK must be
used on systems required to meet SONET/SDH standards. For non-SONET/SDH-compliant systems, loose
tolerances may be used.
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