SLK2701 Datasheet, PDF (1/21 Pages) Texas Instruments – OC-48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER

SLK2701
OCĆ48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER
D Fully Integrated SONET/SDH Transceiver to
Support Clock/Data Recovery and
Multiplexer/Demultiplexer Functions
D Supports OC-48, OC-24, OC-12, Gigabit
Ethernet, and OC-3 Data Rate With Autorate
Detection
D Supports Transmit Only, Receiver Only,
Transceiver and Repeater Functions in a
Single Chip Through Configuration Pins
D Supports SONET/SDH Frame Detection
D On-Chip PRBS Generation and Verification
D Supports 4-Bit LVDS (OIF99.102) Electrical
Interface
D Parity Checking and Generation for the
LVDS Interface
D Single 2.5-V Power Supply
D Interfaces to Back Plane, Copper Cables, or
Optical Modules
SLLS518 − DECEMBER 2001
D Hot Plug Protection
D Low Jitter PECL-Compatible Differential
Serial Interface With Programmable
De-Emphasis for the Serial Output
D On-Chip Termination for LVDS and
PECL-Compatible Interface
D Receiver Differential Input Thresholds
150 mV Minimum
D Supports SONET Loop Timing
D Low Power <900 mW at OC-48 Data Rate
D ESD Protection >2 kV
D 622-MHz Reference Clock
D Maintains Clock Output in Absence of Data
D Local and Remote Loopback
D 100-Pin PZP Package With PowerPad
Design
D Supports FEC Data Rate of 2.7 Gbps
description
The SLK2701 device is a single chip, multirate transceiver that derives high-speed timing signals for SONET/
SDH-based equipment. The device performs clock and data recovery, serial-to-parallel/parallel-to-serial
conversion, and a frame detection function conforming to the SONET/SDH standards.
The device can be configured to operate under OC-48, OC-24, OC-12, or OC-3 data rate through the rate
selection pins or the autorate detection function. An external reference clock operating at 622.08 MHz is
required for the recovery loop, and it also provides a stable clock source in the absence of serial data transitions.
The SLK2701 device accepts 4-bit LVDS parallel data/clock and generates a NRZ SONET/SDH-compliant
signal at the OC-3, OC-12, OC-24, or OC-48 data rate. It also recovers the data and clock from the serial SONET
stream and demultiplexes it into 4-bit LVDS parallel data for full duplex operation. TXDATA0 and RXDATA0 are
the first bits that are transmitted and received in time, respectively. The serial interface is a low jitter,
PECL-compatible differential interface.
The SLK2701 device supports an FEC data rate up to 2.7 Gbps when configured to operate at the OC-48 data
rate and provided with an external reference clock that is properly scaled.
The SLK2701 device provides a comprehensive suite of built-in tests for self-test purposes including local and
remote loopback and pseudorandom bit stream (PRBS) (2⁷-1) generation and verification.
The device comes in a 100-pin VQFP package that requires a single 2.5-V supply with 3.3-V tolerant inputs on
the control pins. The SLK2701 device is very power efficient, dissipating less than 900 mW at 2.488 Gbps, the
OC-48 data rate. It is characterised for operation from −40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
TA
PowerPAD QUAD
(PZP)
−40°C to 85°C
SLK2701PZP
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2001, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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