SLK2701 Datasheet, PDF (4/21 Pages) Texas Instruments – OC-48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER

SLK2701
OCĆ48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER
SLLS518 − DECEMBER 2001
Terminal Functions
clock pins
TERMINAL
NAME
NO.
REFCLKP
94
REFCLKN
95
RXCLKP
67
RXCLKN
68
TXCLKP
79
TXCLKN
80
TXCLKSRCP
70
TXCLKSRCN
71
TYPE
DESCRIPTION
LVDS/PECL
compatible input
LVDS output
LVDS input
Differential reference input clock. There is an on-chip 100-Ω termination resistor differentially
placed between REFCLKP and REFCLKN. The dc bias is also provided on-chip for the
ac-coupled case.
Receive data clock. The data on RXDATA(0:3) is on the falling edges of RXCLKP. The interface
of RXDATA(0:3) and RXCLKP is source synchronous (refer to Figure 7).
Transmit data clock. The data on TXDATA(0:3) is latched on the rising edge of TXCLKP.
LVDS output
Transmit clock source. A clock source generated from the SLK2701 device to the downstream
device (i.e., framer) that could be used by the downstream device to transmit data back to the
SLK2701 device. This clock is frequency-locked to the local reference clock.
serial side data pins
TERMINAL
NAME
NO.
SRXDIP
14
SRXDIN
15
STXDOP
9
STXDON
8
TYPE
DESCRIPTION
PECL compatible
input
PECL compatible
output
Receive differential pairs; high-speed serial inputs
Transmit differential pairs; high-speed serial outputs
parallel side data pins
TERMINAL
NAME
NO.
FSYNCP
73
FSYNCN
74
TYPE
LVDS output
RXDATA[0:3]
P/N
RXPARP
RXPARN
TXDATA[0:3]
P/N
TXPARP
TXPARN
66−63 LVDS output
60−57
56 LVDS output
55
88−81 LVDS input
99 LVDS input
98
DESCRIPTION
Frame sync pulse. This signal indicates the frame boundaries of the incoming data stream. If the
frame-detect circuit is enabled, FSYNC pulses for four RXCLKP and RXCLKN clock cycles,
when it detects the framing patterns.
Receive data pins. Parallel data on this bus is valid on the falling edge of RXCLKP (refer to
Figure 7). RXDATA0 is the first bit received in time.
Receive data parity output
Transmit data pins. Parallel data on this bus is clocked on the rising edge of TXCLKP.
TXDATA0 is the first bit transmitted in time.
Transmit data parity input
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