MSP430X47X3_07 Datasheet, PDF (8/76 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430x47x3, MSP430x47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545A − MAY 2007 − REVISED DECEMBER 2007
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
General-Purpose Register R4
General-Purpose Register R5
General-Purpose Register R6
General-Purpose Register R7
General-Purpose Register R8
General-Purpose Register R9
General-Purpose Register R10
General-Purpose Register R11
General-Purpose Register R12
General-Purpose Register R13
General-Purpose Register R14
General-Purpose Register R15
Table 1. Instruction Word Formats
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
e.g. ADD R4,R5
e.g. CALL R8
e.g. JNE
R4 + R5 −−−> R5
PC −−>(TOS), R8−−> PC
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
Register
Indexed
Symbolic (PC relative)
Absolute
Indirect
SD
DD
DD
DD
DD
D
SYNTAX
MOV Rs,Rd
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV &MEM,&TCDAT
MOV @Rn,Y(Rm)
Indirect
autoincrement
D
Immediate
D
MOV @Rn+,Rm
MOV #X,TONI
NOTE: S = source D = destination
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
OPERATION
R10 −−> R11
M(2+R5)−−> M(6+R6)
M(EDE) −−> M(TONI)
M(MEM) −−> M(TCDAT)
M(R10) −−> M(Tab+R6)
M(R10) −−> R11
R10 + 2−−> R10
#45 −−> M(TONI)
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