MSP430X47X3_07 Datasheet, PDF (14/76 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430x47x3, MSP430x47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545A − MAY 2007 − REVISED DECEMBER 2007
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide, literature
number SLAU056.
digital I/O
There are nine 8-bit I/O ports implemented—ports P1 through P5 and P7 through P10.
D All individual I/O bits are independently programmable.
D Any combination of input, output, and interrupt conditions is possible.
D Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
D Read/write access to port-control registers is supported by all instructions.
D Ports P7/P8 and P9/P10 can be accessed word-wise as ports PA and PB respectively.
D Each I/O has an individually programmable pull−up/pull−down resistor.
oscillator and system clock
The clock system in the MSP430x47xx is supported by the FLL+ module that includes support for a 32768-Hz
watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a 8 MHz high frequency crystal
oscillator (XT1) plus a 16 MHz high frequency crystal oscillator (XT2). The FLL+ clock module is designed to
meet the requirements of both low system cost and low-power consumption. The FLL+ features a digital
frequency locked loop (FLL) hardware which in conjunction with a digital modulator stabilizes the DCO
frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on
clock source and stabilizes in less than 6 μs. The FLL+ module provides the following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
D ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, V_CC may not
have ramped to V_CC(min) at that time. The user must insure the default FLL+ settings are not changed until V_CC
reaches V_CC(min). If desired, the SVS circuit can be used to determine when V_CC reaches V_CC(min).
hardware multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs operations
with 32-bit, 24-bit, 16-bit and 8-bit operands. The module is capable of supporting signed and unsigned
multiplication as well as signed and unsigned multiply and accumulate operations.
WDT+ watchdog timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
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