MSP430X47X3_07 Datasheet, PDF (10/76 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430x47x3, MSP430x47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545A − MAY 2007 − REVISED DECEMBER 2007
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g. flash is not programmed) the CPU will
go into LPM4 immediately after power-up.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD
ADDRESS
PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
PC Out−of−Range (see Note 6)
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh 15, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
0FFFCh
14
(Non)maskable
Timer_B3
TBCCR0 CCIFG (see Note 2)
Maskable
0FFFAh
13
Timer_B3
TBCCR1 to TBCCR2 CCIFGs
TBIFG (see Notes 1 and 2)
Maskable
0FFF8h
12
Comparator_A
CAIFG
Maskable
0FFF6h
11
Watchdog Timer
WDTIFG
Maskable
0FFF4h
10
USCI_A0/B0 Receive
UCA0RXIFG (see Note 1),
UCB0RXIFG (SPI mode) or
UCB0STAT UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG (I2C mode)
(see Note 1)
Maskable
0FFF2h
9
USCI_A0/B0 Transmit
UCA0TXIFG (see Note 1),
UCB0TXIFG (SPI mode) or UCB0RXIFG and
UCB0TXIFG (I2C mode)
(see Note 1)
Maskable
0FFF0h
8
SD16_A
SD16CCTLx SD16OVIFG,
SD16CCTLx SD16IFG
(see Notes 1 and 2)
Maskable
0FFEEh
7
Timer_A3
TACCR0 CCIFG (see Note 2)
Maskable
0FFECh
6
Timer_A3
TACCR1 and TACCR2 CCIFGs,
TAIFG (see Notes 1 and 2)
Maskable
0FFEAh
5
I/O Port P1
(Eight Flags)
P1IFG.0 to P1IFG.7
(see Notes 1 and 2)
Maskable
0FFE8h
4
USCI_A1/B1 Receive
UCA1RXIFG (see Notes 1 and 2),
UCB1RXIFG (SPI mode) or
UCB1STAT UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG (I2C mode)
(see Notes 1 and 2)
Maskable
0FFE6h
3
USCI_A1/B1 Transmit
UCA1TXIFG (see Notes 1 and 2),
UCB1TXIFG (SPI mode) or UCB1RXIFG and
UCB1TXIFG (I2C mode)
(see Notes 1 and 2)
Maskable
0FFE4h
2
I/O Port P2
(Eight Flags)
P2IFG.0 to P2IFG.7
(see Notes 1 and 2)
Maskable
0FFE2h
1
Basic Timer1
BTIFG
Maskable
0FFE0h 0, lowest
NOTES:
3. Multiple source flags
4. Interrupt flags are located in the module.
5. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable
it.
6. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh).
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