CDC857 Datasheet, PDF (8/12 Pages) Texas Instruments – 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS

CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
APPLICATION EXAMPLE
≈ 2.5”
≈ 0.6” (Split to Terminator)
SDRAM represents
a capacitive load
CLK
16 pF
CLK
PLL
120 Ω
16 pF
120 Ω
FBIN
FBIN
SDRAM
Stack
VTR
VCP
120 Ω
SDRAM
Stack
0.3”
Figure 2. Clock Structure #2
differential clock signals
Figure 3 shows the differential clocks are directly terminated by a 120-Ω resistor.
VCC
VCC
Device
Under
Test
OUT
OUT
60 Ω
60 Ω
VTR
RT = 120 Ω
VCP
Receiver
Figure 3. Differential Signal Using Direct Termination Resistor
8
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