CDC857 Datasheet, PDF (1/12 Pages) Texas Instruments – 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS

CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
D Phase-Lock Loop Clock Distribution for
Double Data Rate Synchronous DRAM
DGG PACKAGE
(TOP VIEW)
Applications
D Distributes One Differential Clock Input to
Ten Differential Outputs
D External Feedback Pins (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Clock Input
D Operates at V_CC = 2.5 V and AV_CC = 3.3 V
D Packaged in Plastic 48-Pin (DGG) Thin
Shrink Small-Outline Package (TSSOP)
D Spread Spectrum Clocking Tracking
GND 1
Y0 2
Y0 3
V_CC 4
Y1 5
Y1 6
GND 7
GND 8
Y2 ⁹
Y2 ¹⁰
48 GND
47 Y5
46 Y5
45 V_CC
44 Y6
43 Y6
42 GND
41 GND
40 _Y7
39 _Y7
Capability to Reduce EMI
description
V_CC ¹¹
V_CC ¹²
CLK ¹³
38 _VCC
37 _G
36 _FBIN
The CDC857-2 and CDC857-3 are high-perfor-
mance, low-skew, low-jitter, phase-lock loop
(PLL) clock driver. They use a PLL to precisely
align, in both frequency and phase, the feedback
(FBOUT) output to the clock (CLK) input signal.
The CDC857-3 operates at 3.3 V (PLL) and 2.5 V
(output buffer). The CDC857-2 operates at
2.5 V (PLL and output buffer).
One bank of ten inverting and noninverting
outputs provide ten low-skew, low-jitter copies of
CLK. Output signal duty cycles are adjusted to
CLK ¹⁴
V_CC ¹⁵
AV_CC ¹⁶
AGND ¹⁷
GND ¹⁸
Y3 ¹⁹
Y3 ²⁰
V_CC ²¹
Y4 ²²
Y4 ²³
GND ²⁴
35 _FBIN
34 _VCC
33 _FBOUT
32 _FBOUT
31 _GND
30 _Y8
29 _Y8
28 _VCC
27 _Y9
26 _Y9
25 _GND
50%, independent of the duty cycle at CLK.
All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs
switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to high impedance
state (3-state).
Unlike many products containing PLLs, the CDC857 does not require external RC networks. The loop filter for
the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuity, the CDC857 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or
feedback signals. The PLL can be bypassed for test purposes by strapping AV_CC to ground. If AV_CC is at GND
and V_CC = ON, 2 falling edges on G cause the PLL to run with FBOUT being enabled and all other outputs being
disabled, after AV_CC ramps up to its specified V_CC value, with G being kept low. The CDC857 is characterized
for operation from 0°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1999, Texas Instruments Incorporated
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