CDC857 Datasheet, PDF (5/12 Pages) Texas Instruments – 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS

CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX UNIT
VIK
VOH
VOL
IOH
IOL
VO
II
IOZ
Input voltage
All input pins
High-level output voltage
Low-level output voltage
High-level output current
Low-level output current
Output voltage swing
Input current
G
CLK, FBIN
High-impedance output current
VCC = 2.3 V,
II = –18 mA
VCC = min to max, IOH= –1 mA
VCC = 2.3 V,
IOH ₌ –12 mA
VCC = min to max, IOL = 1 mA
VCC = 2.3 V,
IOL = 12 mA
VCC = 2.3 V,
VO = 1 V
VCC = 2.3 V,
VO = 1.2 V
For load condition see Figure 3
VCC = 2.7 V,
VCC = 2.7 V,
VCC = 2.7 V,
VI = 0 V to 2.7 V
VI = 0 V to 2.7 V
VO = VCC or GND
VCC–0.1
1.7
–18
26
1.1
–1.2 V
V
0.1
V
0.6
–32
mA
35
mA
VCC–0.4 V
±10
±10 ^µA
±10 µA
VOC
Output crossing point voltage‡
(VCC/2)–
0.1
VCC/2
(VCC/2)+
0.1
V
ICCZ
Supply current, disabled
AVCC and VCC = max,
G = L or no input CLK signal
500
800 µA
lCC
Supply current on VCC
(see Figure 7)
VCC = 2.7 V,
fO = 167 MHz,
All outputs switching 16 pF in 60 Ω
environment,
See Figure 3
235
300 mA
AICC
Supply current on
AVCC
CDC857–2
CDC857–3
AVCC = 2.7 V,
AVCC = 3.6 V,
fO = 167 MHz
fO = 167 MHz
9
12
mA
15
19
CI
Input capacitance
VCC = 2.5 V,
VI = VCC or GND
2
pF
CO
Output capacitance
VCC = 2.5 V,VO = VCC or GND
3
pF
† _{All typical values are at respective nominal VCC.}
‡ _{The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120-Ω resistor, where VTR is the true input}
signal voltage and VCP is the complementary input signal voltage (see Figure 3).
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