CDC857 Datasheet, PDF (3/12 Pages) Texas Instruments – 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS

CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
SPECIAL TEST MODES
INPUTS
OUTPUTS
VCC
AVCC
G
CLK†
Y
Y
FBOUT
ON
0V
L
L
Z
Z
Z
ON
0V
L
H
Z
Z
Z
ON
0V
H
L
L
H
L
ON
0V
H
H
H
L
H
ON
UP‡
↓^§
L
Z
Z
L
ON
UP‡
↓^§
H
Z
Z
H
† _{Only one signal shown for this differential input.}
‡ _{AVCC ramped up after two (2) high-to-low transitions on G input & G being low.}
§ _{At least two (2) high-to-low transitions during AVCC = 0.}
FBOUT
Z
Z
H
L
H
L
COMMENTS
Clock Mode
Clock Mode
Clock Mode
Clock Mode
PLL Mode
PLL Mode
Terminal Functions
TERMINAL
NAME
NO.
AGND
17
AVCC
16
CLK
13
CLK
14
FBIN
36
FBIN
35
FBOUT
32
FBOUT
33
G
37
GND
VCC
Y0, Y1, Y2,
Y3, Y4, Y5,
Y6, Y7, Y8,
Y9
Y0, Y1, Y2,
Y3, Y4, Y5,
Y6, Y7, Y8,
Y9
1, 7, 8, 18,
24, 25, 31,
41, 42, 48
4, 11, 12,
15, 21, 28,
34, 38, 45
3, 5, 10,
20, 22, 46,
44, 39, 29,
27
2, 6, 9,
19, 23, 47,
43, 40, 30,
26
I/O
DESCRIPTION
Ground
Power
I
I
O
I
Ground
Analog ground. AGND provides the ground reference for the analog circuitry.
Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC
can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed
and CLK is buffered directly to the device outputs. During disable (G = 0), the PLL is powered down.
Clock input, CLK provides the clock signal to be distributed by the CDC857 clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK
must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is
powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase
lock the feedback signal to its reference signal.
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired
to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL.
Output bank enable. G is the output enable for outputs Y and Y. When G is low outputs Y are disabled
to a high-impedance state. When G is high, all outputs Y are enabled and switch at the same
frequency as CLK.
Ground
Power Power supply
O
Clock outputs. These outputs provide low-skew copies of CLK.
O
Clock outputs. These outputs provide low-skew copies of CLK.
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