CDC857 Datasheet, PDF (7/12 Pages) Texas Instruments – 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS

CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
APPLICATION EXAMPLE
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
Table 1. Clock Structure and SDRAM Loads per Clock
CLOCK
STRUCTURE
NUMBER of
SDRAM LOADS
PER CLOCK
1
2
2
4
CAPACITIVE LOADING ON
THE PLL OUTPUTS (pF)
MIN
MAX
5
8
10
16
≈ 2.5”
≈ 0.6” (Split to Terminator)
SDRAM represents
a capacitive load
SDRAM
CLK
16 pF
CLK
16 pF
PLL
120 Ω
120 Ω
FBIN
FBIN
VTR
VCP
120 Ω
SDRAM
0.3”
Figure 1. Clock Structure #1
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